Inventor
KELLAR SCOT A
US14 patents
Patents
14 patentsUS7157787B2Jan 2, 2007
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
INTEL CORP867 citations99
US7056807B2Jun 6, 2006
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP245 citations99
US7037804B2May 2, 2006
Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration
INTEL CORP258 citations99
US6975016B2Dec 13, 2005
Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
INTEL CORP252 citations99
US6887769B2May 3, 2005
Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
INTEL CORP516 citations99
US6762076B2Jul 13, 2004
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
INTEL CORP579 citations99
US6661085B2Dec 9, 2003
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP536 citations99
US6911373B2Jun 28, 2005
Ultra-high capacitance device based on nanostructures
INTEL CORP32 citations96
US7265406B2Sep 4, 2007
Capacitor with conducting nanostructure
INTEL CORP12 citations92
US6599808B2Jul 29, 2003
Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode
INTEL CORP24 citations92
US7091084B2Aug 15, 2006
Ultra-high capacitance device based on nanostructures
INTEL CORP11 citations84
US7271434B2Sep 18, 2007
Capacitor with insulating nanostructure
INTEL CORP7 citations74
US7244983B2Jul 17, 2007
Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode
INTEL CORP9 citations74
US10068866B2Sep 4, 2018
Integrated circuit package having rectangular aspect ratio
INTEL CORP0 citations41