Inventor
RAVISHANKAR MOSUR K
US10 patents
⚠️ This page may combine multiple inventors who share the name “RAVISHANKAR MOSUR K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEWLETT PACKARD DEVELOPMENT CO
9 patentsUS6697919B2Feb 24, 2004
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO108 citations97
US6675265B2Jan 6, 2004
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
HEWLETT PACKARD DEVELOPMENT CO93 citations97
US6636949B2Oct 21, 2003
System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
HEWLETT PACKARD DEVELOPMENT CO80 citations97
US6622217B2Sep 16, 2003
Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO114 citations97
US6751710B2Jun 15, 2004
Scalable multiprocessor system and cache coherence method
HEWLETT PACKARD DEVELOPMENT CO23 citations92
US6748498B2Jun 8, 2004
Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector
HEWLETT PACKARD DEVELOPMENT CO31 citations92
US7389389B2Jun 17, 2008
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO12 citations84
US6622218B2Sep 16, 2003
Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system
HEWLETT PACKARD DEVELOPMENT CO18 citations83
US6925537B2Aug 2, 2005
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
HEWLETT PACKARD DEVELOPMENT CO11 citations73