Inventor

SAVOJ JAFAR

US72 patents

⚠️ This page may combine multiple inventors who share the name “SAVOJ JAFAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAVOJ JAFAR

APPLE INC

Reference voltage circuit with flipped-gate transistor

Supply voltage envelope detection

Low latency comparator with local clock circuit

Chip to chip interface with scalable bandwidth

On-chip parameter measurement

Hybrid serial receiver circuit

Latency reduction in analog-to-digital converter-based receiver circuits

Noise reduction in oscillator-based sensor circuits

Highly granular voltage regulator

Digital sensor with embedded reference clock

High output impedance current mirror circuit

Feedforward cancellation circuit

On-chip supply ripple tolerant clock distribution

On-chip supply ripple tolerant clock distribution

Reference circuit for metrology system

Chip to chip interface with scalable bandwidth

Reference circuit for metrology system

MARVELL INT LTD

High-precision signal detection for high-speed receiver

Circuitry for eliminating false lock in delay-locked loops

Method and apparatus for performing transmit pre-emphasis

Retiming circuits for phase-locked loops

High-precision signal detection for high-speed receiver

Device and method for frequency synthesis for wireline transceivers and similar devices

Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters

Method and apparatus for performing transmit pre-emphasis

SAVOJ JAFAR

Clock and data recovery for NFC transceivers

Clock and data recovery circuit with decision feedback equalization

LR polyphase filter

Adaptive NFC transceivers

High-precision signal detection for high-speed receiver

NFC transceiver with current converter

NFC transceiver utilizing common circuitry for active and passive modes

RAMBUS INC

Receiver with enhanced clock and data recovery

Receiver with enhanced clock and data recovery

Receiver with enhanced clock and data recovery

Receiver with enhanced clock and data recovery

Receiver with enhanced clock and data recovery

XILINX INC

Injection-controlled-locked phase-locked loop

Data receivers and methods of implementing data receivers in an integrated circuit

Wide frequency range clock generation using a single oscillator

BROADCOM CORP

Linear half-rate phase detector and clock and data recovery circuit

Linear half-rate phase detector and clock and data recovery circuit

LEE HAE-CHANG

Receiver with enhanced clock and data recovery

QUALCOMM INC

LO generation and distribution in a multi-band transceiver

AHMADI MAHMOUD R

Frequency synthesizer noise reduction

PARK DONGMIN

Method and apparatus for receiver adaptive phase clocked low power serial link

LIM SIOK WEI

Receiver having a wide common mode input range

SOLTANIAN BABAK

Low power complementary logic latch and RF divider

TAGHIVAND MAZHAREDDIN

Frequency divider circuit

MARCU CRISTIAN

Adaptive signal scaling in NFC transceivers