Inventor

HEBIG TRAVIS R

US45 patents

⚠️ This page may combine multiple inventors who share the name “HEBIG TRAVIS R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEBIG TRAVIS R

IBM

Single ended sensing circuits for signal lines

Power management SRAM write bit line drive circuit

Power management domino SRAM bit line discharge circuit

Method and apparatus for multi-word write in domino read SRAMs

Circuit for improved SRAM write around with reduced read access penalty

Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system

Leakage reduction in output driver circuits

Partial update in a ternary content addressable memory

Implementing low temperature wafer test

Two phase search content addressable memory with power-gated main-search

Data security for dynamic random access memory using body bias to clear data at power-up

Method and apparatus to limit circuit delay dependence on voltage for single phase transition

Method and apparatus to limit circuit delay dependence on voltage

Self-timed, single-ended sense amplifier

Level shifter for a time-varying input

Level shifter for a time-varying input

Partial update in a ternary content addressable memory

Integrated decoupling capacitor utilizing through-silicon via

Integrated decoupling capacitor utilizing through-silicon via

Recyclate verification

Removal of HAB-produced toxins from bodies of water

Recyclate verification

Recyclate verification

Removal of HAB-produced toxins from bodies of water

Recyclate verification

Binding Bisphenol A in a polycarbonate container

Layout to minimize FET variation in small dimension photolithography

Assessing resources required to complete a VLSI design

Apparatus for guaranteed write through in domino read SRAM&#39;s

Memory array pulse width control

BEHRENDS DERICK G

Implementing mulitple mask lithography timing variation mitigation

Data dependent SRAM write assist

Implementing power saving self powering down latch structure

Implementing RC and coupling delay correction for SRAM

Data security for dynamic random access memory at power-up

Implementing single bit redundancy for dynamic SRAM circuit with any bit decode

Single cycle data copy for two-port SRAM

FREIBURGER PETER T

SRAM local evaluation logic for column selection

SRAM local evaluation and write logic for column selection

ADAMS CHAD A

Implementing column redundancy steering for memories with wordline repowering

High-speed testing of integrated devices

AVAGO TECHNOLOGIES GENERAL IP

Method and apparatus for selective write assist using shared boost capacitor

ARSOVSKI IGOR

Content addressable memory early-predict late-correct single ended sensing

HEBIG TRAVIS R

Tamper resistant electronic system utilizing acceptable tamper threshold count

GLOBALFOUNDRIES INC

Detecting water intrusion in electronic devices

Apparatus for guaranteed write through in domino read SRAM's