Inventor
PAREDES JOSE ANGEL
US25 patents
Patents
25 patentsUS6826090B1Nov 30, 2004
Apparatus and method for a radiation resistant latch
IBM21 citations92
US6640293B1Oct 28, 2003
Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays
IBM21 citations92
US6477635B1Nov 5, 2002
Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing
IBM25 citations92
US7467325B2Dec 16, 2008
Processor instruction retry recovery
IBM26 citations91
US7202704B2Apr 10, 2007
Leakage sensing and keeper circuit for proper operation of a dynamic circuit
IBM14 citations84
US6825691B1Nov 30, 2004
Apparatus and method for a radiation resistant latch with integrated scan
IBM19 citations84
US7827443B2Nov 2, 2010
Processor instruction retry recovery
IBM12 citations83
US6934181B2Aug 23, 2005
Reducing sub-threshold leakage in a memory array
IBM9 citations74
US6914450B2Jul 5, 2005
Register-file bit-read method and apparatus
IBM8 citations74
US6353558B1Mar 5, 2002
Method and apparatus for writing to memory cells
IBM6 citations72
US7679973B2Mar 16, 2010
Register file
IBM5 citations71
US7443737B2Oct 28, 2008
Register file
IBM5 citations71
US7116569B2Oct 3, 2006
Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask
IBM7 citations71
US7506230B2Mar 17, 2009
Transient noise detection scheme and apparatus
IBM6 citations63
US7012839B1Mar 14, 2006
Register file apparatus and method incorporating read-after-write blocking using detection cells
IBM4 citations63
US7002860B2Feb 21, 2006
Multilevel register-file bit-read method and apparatus
IBM4 citations63
US7478276B2Jan 13, 2009
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
IBM4 citations62
US6737888B1May 18, 2004
Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement
IBM5 citations62
US6341095B1Jan 22, 2002
Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation
IBM6 citations62
US6236253B1May 22, 2001
Apparatus and method for controlling a reset in a self-timed circuit of a multiple-clock system
IBM5 citations62
US7085896B2Aug 1, 2006
Method and apparatus which implements a multi-ported LRU in a multiple-clock system
IBM3 citations59
US7142463B2Nov 28, 2006
Register file method incorporating read-after-write blocking using detection cells
IBM0 citations52
US7683662B2Mar 23, 2010
Method and apparatus for implementing complex logic within a memory array
IBM1 citations49
US7471103B2Dec 30, 2008
Method for implementing complex logic within a memory array
IBM1 citations49
US7015723B2Mar 21, 2006
Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation
IBM0 citations42