Inventor

SOLIHIN YAN

US57 patents

⚠️ This page may combine multiple inventors who share the name “SOLIHIN YAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SOLIHIN YAN

EMPIRE TECHNOLOGY DEV LLC

Aggregating cache eviction notifications to a directory

Methods and systems for dynamic DRAM cache sizing

Multi-granular cache coherence

Accelerating cache state transfer on a directory-based multicore architecture

Shared cache data movement in thread migration

Thread and data assignment in multi-core processors based on cache miss data

Cache partitioning in a multicore processor

One-cacheable multi-core architecture

Operations related to a retransmission buffer

Memory allocation accelerator

Cache partitioning in a multicore processor

Circuit switch pre-reservation in an on-chip network

Cache partitioning in a multicore processor

Increased refresh interval and energy efficiency in a DRAM

Thread and data assignment in multi-core processors based on cache miss data and thread category

Magnetoresistive random-access memory cache write management

Hardware-based array compression

Energy-efficient dynamic dram cache sizing via selective refresh of a cache in a dram

Memory allocation accelerator

Increased refresh interval and energy efficiency in a DRAM

Resource allocation in multi-core architectures

Low power execution of a multithreaded program

Cache coherence directory in multi-processor architectures

Balanced processing using heterogeneous cores

Core prioritization for heterogeneous on-chip networks

Directory coherence for multicore processors

Data storage based on memory persistency

Heterogeneous magnetic memory architecture

Memory initialization using cache state

Dynamic router power control in multi-core processors

Performance and energy efficiency while using large pages

SOLIHIN YAN

Balanced processing using heterogeneous cores

Data storage and access in multi-core processor architectures

Multiprocessor cache prefetch with off-chip bandwidth allocation

Hardware-base accelerator for managing copy-on-write of multi-level caches utilizing block copy-on-write differential update table

Hardware-based array compression

Sectored cache with a tag structure capable of tracking sectors of data stored for a particular cache way

Multi-core processor cache coherence for reduced off-chip traffic

Energy conservation in a multicore chip

Managing addressable memory in heterogeneous multicore processors

Cache coherence directory in multi-processor architectures

Virtual cache directory in multi-processor architectures

Resource allocation in multi-core architectures

Quality of service targets in multicore processors

Accelerating cache state transfer on a directory-based multicore architecture

Domain based cache coherence protocol

Low power execution of a multithreaded program

Data storage and access in multi-core processor architectures

UNIV NORTH CAROLINA STATE

Systems and methods for modeling memory access behavior and memory traffic timing behavior

UNIV CENTRAL FLORIDA RES FOUND INC

Methods of crash recovery for data stored in non-volatile main memory