Inventor

CHACHAD ABHIJEET ASHOK

US96 patents

⚠️ This page may combine multiple inventors who share the name “CHACHAD ABHIJEET ASHOK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHACHAD ABHIJEET ASHOK

TEXAS INSTRUMENTS INC

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Handling non-correctable errors

Write control for read-modify-write operations in cache memory

Handling non-correctable errors

Error correcting codes for multi-master memory controller

Pipelined read-modify-write operations in cache memory

Merging data for write allocate

Lookahead priority collection to support priority elevation

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Zero cycle clock invalidate operation

Cache size change

Global coherence operations

Tag update bus for updated coherence state

Pipelined read-modify-write operations in cache memory

Programmable address-based write-through cache control

Lookahead priority collection to support priority elevation

Hardware coherence for memory controller

Hardware coherence signaling protocol

Cache coherence shared state suppression

Hardware coherence signaling protocol

Error correcting codes for multi-master memory controller

Shadow caches for level 2 cache controller

Hardware coherence for memory controller

Cache coherence shared state suppression

Pipelined read-modify-write operations in cache memory

Lookahead priority collection to support priority elevation

Cache preload operations using streaming engine

Cache coherence shared state suppression

Memory pipeline control in a hierarchical memory system

Cache management operations using streaming engine

Shadow caches for level 2 cache controller

Hardware coherence for memory controller

Cache preload operations using streaming engine

Cache management operations using streaming engine

Cache size change

Cache size change

Prefetch management in a hierarchical cache system

Prefetch kill and revival in an instruction cache

Tag update bus for updated coherence state

Hardware coherence signaling protocol

Write streaming with cache write acknowledgment in a processor

Controller with caching and non-caching modes

Handling non-correctable errors

CHACHAD ABHIJEET ASHOK

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

Cache with multiple access pipelines

DAMODARAN RAGURAM

Requester based transaction status reporting in a system with multi-level memory

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

TRAN JONATHAN SON HUNG

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

ZBICIAK JOSEPH RAYMOND MICHAEL

Priority based exception mechanism for multi-level cache controller