Inventor
WALLER MARK
GB34 patents
⚠️ This page may combine multiple inventors who share the name “WALLER MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PULSIC LTD
19 patentsUS7257797B1Aug 14, 2007
Method of automatic shape-based routing of interconnects in spines for integrated circuit design
PULSIC LTD62 citations98
US7784010B1Aug 24, 2010
Automatic routing system with variable width interconnect
PULSIC LTD45 citations96
US7363607B2Apr 22, 2008
Method of automatically routing nets according to parasitic constraint rules
PULSIC LTD34 citations96
US7131096B1Oct 31, 2006
Method of automatically routing nets according to current density rules
PULSIC LTD59 citations96
US8966425B1Feb 24, 2015
Clock tree generation and routing
PULSIC LTD44 citations93
US8751996B1Jun 10, 2014
Automatically routing nets according to parasitic constraint rules
PULSIC LTD19 citations92
US7823113B1Oct 26, 2010
Automatic integrated circuit routing using spines
PULSIC LTD26 citations92
US7802208B1Sep 21, 2010
Design automation using spine routing
PULSIC LTD23 citations92
US7657852B2Feb 2, 2010
System and technique of pattern matching and pattern replacement
PULSIC LTD34 citations92
US7603644B2Oct 13, 2009
Integrated circuit routing and compaction
PULSIC LTD15 citations92
US7530040B1May 5, 2009
Automatically routing nets according to current density rules
PULSIC LTD15 citations92
US8707239B2Apr 22, 2014
Integrated circuit routing with compaction
PULSIC LTD5 citations84
US7373628B1May 13, 2008
Method of automatically routing nets using a Steiner tree
PULSIC LTD13 citations84
US8788999B1Jul 22, 2014
Automatic routing system with variable width interconnect
PULSIC LTD5 citations83
US8010928B1Aug 30, 2011
Automatically routing nets according to parasitic constraint rules
PULSIC LTD5 citations74
US11200363B1Dec 14, 2021
Optimizing place-and-routing using a random normalized polish expression
PULSIC LTD2 citations71
US10726184B1Jul 28, 2020
Method for optimizing place-and-routing using a random normalized polish expression
PULSIC LTD3 citations71
US7984411B2Jul 19, 2011
Integrated circuit routing and compaction
PULSIC LTD1 citations63
US12032893B2Jul 9, 2024
Optimizing place-and-routing using a random normalized polish expression
PULSIC LTD0 citations61
MAKERBOT IND LLC
5 patentsUS9248600B2Feb 2, 2016
Build platform leveling and homing
MAKERBOT IND LLC37 citations94
US9555585B2Jan 31, 2017
Build platform leveling and homing
MAKERBOT IND LLC3 citations73
US11571852B2Feb 7, 2023
Multi-filament three-dimensional printing
MAKERBOT IND LLC2 citations71
US10773511B2Sep 15, 2020
Filament swapping in three-dimensional printing
MAKERBOT IND LLC0 citations49
US10500837B2Dec 10, 2019
Filament swapping in three-dimensional printing
MAKERBOT IND LLC0 citations49
WALLER MARK
5 patentsUS8479141B1Jul 2, 2013
Automation using spine routing
WALLER MARK13 citations92
US8099700B1Jan 17, 2012
Automatic integrated circuit routing using spines
WALLER MARK20 citations92
US8490036B2Jul 16, 2013
System and technique of pattern matching and pattern replacement
WALLER MARK9 citations83
US9940421B1Apr 10, 2018
Method for optimizing place-and-routing using a random normalized polish expression
WALLER MARK5 citations82
US8332799B2Dec 11, 2012
Integrated circuit routing with compaction
WALLER MARK0 citations51
BIRCH JEREMY
3 patentsUS8095903B2Jan 10, 2012
Automatically routing nets with variable spacing
BIRCH JEREMY22 citations92
US8949760B2Feb 3, 2015
Automatically routing nets with variable spacing
BIRCH JEREMY11 citations83
US8332805B1Dec 11, 2012
Automatically routing nets according to parasitic constraint rules
BIRCH JEREMY8 citations83