Inventor

STEIGERWALD JOSEPH M

US28 patents

⚠️ This page may combine multiple inventors who share the name “STEIGERWALD JOSEPH M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEIGERWALD JOSEPH M

INTEL CORP

Self-aligned contacts

Logic chip including embedded magnetic tunnel junctions

Self-aligned contacts

Use of a polish stop layer in the formation of metal structures

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Logic chip including embedded magnetic tunnel junctions

Logic chip including embedded magnetic tunnel junctions

Multi-threshold voltage devices and associated techniques and configurations

Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations

Logic chip including embedded magnetic tunnel junctions

Self-aligned contacts

Self-aligned contacts

Multi-threshold voltage devices and associated techniques and configurations

Self-aligned contacts

Self-aligned contacts

Electrochemically polishing conductive films on semiconductor wafers

Multi-threshold voltage devices and associated techniques and configurations

BOHR MARK T

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

STEIGERWALD JOSEPH M

Polish to remove topography in sacrificial gate layer prior to gate patterning

Methods to form memory devices having a capacitor with a recessed electrode

SONY GROUP CORP

Multi-threshold voltage devices and associated techniques and configurations

Multi-threshold voltage devices and associated techniques and configurations

RENSSELAER POLYTECH INST

Systems for performing chemical mechanical planarization and process for conducting same

LINDERT NICK

Formation of DRAM capacitor among metal interconnect