Inventor

SINGH JAGAR

US95 patents

⚠️ This page may combine multiple inventors who share the name “SINGH JAGAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINGH JAGAR

GLOBALFOUNDRIES INC

LDMOS FinFET structures with trench isolation in the drain extension

Integration of gate structures and spacers with air gaps

LDMOS finFET structures with multiple gate structures

Resistor and capacitor disposed directly upon a SAC cap of a gate structure of a semiconductor structure

Fin-based RF diodes

Non-planar schottky diode and method of fabrication

Method for making high voltage integrated circuit devices in a fin-type process and resulting devices

Semiconductor fuses and fabrication methods thereof

Three-dimensional electrostatic discharge semiconductor device

Devices and methods of forming higher tunability FinFET varactor

LDMOS finFET structures with shallow trench isolation inside the fin

Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same

Fin-based RF diodes

Bipolar junction transistors and methods of fabrication

Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure

Parasitic lateral bipolar transistor with improved ideality and leakage currents

Method for making high voltage integrated circuit devices in a fin-type process and resulting devices

Methods of fabricating nanowire structures

Device and method for a LDMOS design for a FinFET integrated circuit

Method for fabricating integrated circuits including contacts for metal resistors

High-voltage and analog bipolar devices

Metallization layers configured for reduced parasitic capacitance

Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors

Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors

Split well zero threshold voltage field effect transistor for integrated circuits

Fin diode with increased junction area

Three-dimensional electrostatic discharge semiconductor device

Three-dimensional electrostatic discharge semiconductor device

GLOBALFOUNDRIES US INC

Fin-based lateral bipolar junction transistor with reduced base resistance and method

Method for forming lateral heterojunction bipolar devices and the resulting devices

Laterally diffused metal-oxide semiconductor with gate contact

Lateral bipolar transistors

Lateral bipolar transistor structure with base over semiconductor buffer and related method

Bipolar junction transistors including wrap-around emitter and collector contacts

Structure with inductor embedded in bonded semiconductor substrates and methods

Lateral bipolar transistor with gated collector

Lateral bipolar transistor

Lateral bipolar transistor with gated collector

Bipolar junction transistors including a portion of a base layer inside a cavity in a dielectric layer

Lateral bipolar transistor

Lateral bipolar transistor

Lateral bipolar junction transistor including a stress layer and method

Lateral bipolar transistor

Bipolar junction transistors including a stress liner

Non-self-aligned lateral bipolar junction transistors

Structure with polycrystalline active region fill shape(s), and related method

Structure providing charge controlled electronic fuse

Gate controlled lateral bipolar junction/heterojunction transistors

AGENCY SCIENCE TECH & RES

Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration

COYNE EDWARD JOHN

Field effect transistors having improved breakdown voltages and methods of forming the same