P

Inventor

DOYLE PETER L

US58 patents
⚠️ This page may combine multiple inventors who share the name “DOYLE PETER L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

44 patents
US6885374B2Apr 26, 2005

Apparatus, method and system with a graphics-rendering engine having a time allocator

INTEL CORP68 citations98
US6867779B1Mar 15, 2005

Image rendering

INTEL CORP48 citations96
US7173627B2Feb 6, 2007

Apparatus, method and system with a graphics-rendering engine having a graphics context manager

INTEL CORP11 citations84
US6954208B2Oct 11, 2005

Depth write disable for rendering

INTEL CORP13 citations84
US7280113B1Oct 9, 2007

Multiple texture compositing

INTEL CORP11 citations83
US6995773B2Feb 7, 2006

Automatic memory management

INTEL CORP7 citations74
US6950108B2Sep 27, 2005

Bandwidth reduction for rendering using vertex data

INTEL CORP5 citations74
US6762765B2Jul 13, 2004

Bandwidth reduction for zone rendering via split vertex buffers

INTEL CORP11 citations74
US6747658B2Jun 8, 2004

Automatic memory management for zone rendering

INTEL CORP9 citations74
US6747657B2Jun 8, 2004

Depth write disable for zone rendering

INTEL CORP7 citations74
US6747653B2Jun 8, 2004

Efficient object storage for zone rendering

INTEL CORP5 citations74
US6738069B2May 18, 2004

Efficient graphics state management for zone rendering

INTEL CORP8 citations74
US11269409B2Mar 8, 2022

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

INTEL CORP2 citations73
US10930060B2Feb 23, 2021

Conditional shader for graphics

INTEL CORP2 citations73
US10649524B2May 12, 2020

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

INTEL CORP4 citations73
US10204393B2Feb 12, 2019

Pre-pass surface analysis to achieve adaptive anti-aliasing modes

INTEL CORP3 citations73
US10152632B2Dec 11, 2018

Dynamic brightness and resolution control in virtual environments

INTEL CORP4 citations73
US10068307B2Sep 4, 2018

Command processing for graphics tile-based rendering

INTEL CORP2 citations73
US9953395B2Apr 24, 2018

On-die tessellation distribution

INTEL CORP5 citations73
US9741154B2Aug 22, 2017

Recording the results of visibility tests at the input geometry object granularity

INTEL CORP3 citations73
US9396032B2Jul 19, 2016

Priority based context preemption

INTEL CORP5 citations73
US10970538B2Apr 6, 2021

Dynamic brightness and resolution control in virtual environments

INTEL CORP2 citations72
US6731297B1May 4, 2004

Multiple texture compositing

INTEL CORP7 citations72
US6429873B1Aug 6, 2002

Addressing of monolithic texture maps

INTEL CORP7 citations72
US9824412B2Nov 21, 2017

Position-only shading pipeline

INTEL CORP5 citations70
US11398006B2Jul 26, 2022

Pre-pass surface analysis to achieve adaptive anti-aliasing modes

INTEL CORP0 citations63
US11004265B2May 11, 2021

Adaptive sub-patches system, apparatus and method

INTEL CORP0 citations63
US10891705B2Jan 12, 2021

Pre-pass surface analysis to achieve adaptive anti-aliasing modes

INTEL CORP0 citations63
US10242496B2Mar 26, 2019

Adaptive sub-patches system, apparatus and method

INTEL CORP1 citations63
US9087392B2Jul 21, 2015

Techniques for efficient GPU triangle list adjacency detection and handling

INTEL CORP3 citations63
US7348986B2Mar 25, 2008

Image rendering

INTEL CORP3 citations63
US7164427B2Jan 16, 2007

Apparatus, method and system with a graphics-rendering engine having a time allocator

INTEL CORP4 citations63
US12436727B2Oct 7, 2025

Regional adjustment of render rate

INTEL CORP0 citations62
US12061831B2Aug 13, 2024

Regional adjustment of render rate

INTEL CORP0 citations62
US11941169B2Mar 26, 2024

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

INTEL CORP0 citations62
US11816384B2Nov 14, 2023

Regional adjustment of render rate

INTEL CORP0 citations62
US11551400B2Jan 10, 2023

Apparatus and method for optimized tile-based rendering

INTEL CORP1 citations62
US11531510B2Dec 20, 2022

Regional adjustment of render rate

INTEL CORP0 citations62
US11514721B2Nov 29, 2022

Dynamic brightness and resolution control in virtual environments

INTEL CORP0 citations62
US11099800B2Aug 24, 2021

Regional adjustment of render rate

INTEL CORP0 citations62
US11094102B2Aug 17, 2021

Write out stage generated bounding volumes

INTEL CORP0 citations62
US10242494B2Mar 26, 2019

Conditional shader for graphics

INTEL CORP1 citations61
US10691392B2Jun 23, 2020

Regional adjustment of render rate

INTEL CORP0 citations52
US10572966B2Feb 25, 2020

Write out stage generated bounding volumes

INTEL CORP0 citations52

DIGITAL EQUIPMENT CORP

4 patents

DOYLE PETER L

2 patents

Showing the top 50 of 58 patents by PatentIndex Score.