Inventor
HUANG SHUANGWU
SG21 patents
⚠️ This page may combine multiple inventors who share the name “HUANG SHUANGWU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
7 patentsUS7485562B2Feb 3, 2009
Method of making multichip wafer level packages and computing systems incorporating same
MICRON TECHNOLOGY INC141 citations99
US6964881B2Nov 15, 2005
Multi-chip wafer level system packages and methods of forming same
MICRON TECHNOLOGY INC51 citations96
US6825553B2Nov 30, 2004
Multichip wafer level packages and computing systems incorporating same
MICRON TECHNOLOGY INC44 citations96
US7087992B2Aug 8, 2006
Multichip wafer level packages and computing systems incorporating same
MICRON TECHNOLOGY INC21 citations92
US6987031B2Jan 17, 2006
Multiple chip semiconductor package and method of fabricating same
MICRON TECHNOLOGY INC27 citations92
US6958537B2Oct 25, 2005
Multiple chip semiconductor package
MICRON TECHNOLOGY INC32 citations92
US7553697B2Jun 30, 2009
Multiple chip semiconductor package
MICRON TECHNOLOGY INC1 citations63
PAGAILA REZA A
7 patentsUS8742579B2Jun 3, 2014
Semiconductor device and method of providing Z-interconnect conductive pillars with inner polymer core
PAGAILA REZA A101 citations98
US8193034B2Jun 5, 2012
Semiconductor device and method of forming vertical interconnect structure using stud bumps
PAGAILA REZA A72 citations98
US8133762B2Mar 13, 2012
Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
PAGAILA REZA A84 citations98
US8258010B2Sep 4, 2012
Making a semiconductor device having conductive through organic vias
PAGAILA REZA A41 citations94
US9236352B2Jan 12, 2016
Semiconductor die and method of forming noise absorbing regions between THVs in peripheral region of the die
PAGAILA REZA A6 citations82
US9263361B2Feb 16, 2016
Semiconductor device having a vertical interconnect structure using stud bumps
PAGAILA REZA A4 citations73
US8093151B2Jan 10, 2012
Semiconductor die and method of forming noise absorbing regions between THVS in peripheral region of the die
PAGAILA REZA A3 citations61
STATS CHIPPAC LTD
3 patentsUS8017515B2Sep 13, 2011
Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
STATS CHIPPAC LTD49 citations94
US9640504B2May 2, 2017
Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
STATS CHIPPAC LTD4 citations84
US9443762B2Sep 13, 2016
Semiconductor device and method of forming a thin wafer without a carrier
STATS CHIPPAC LTD2 citations63