Inventor

GOEL MANISH

US79 patents

⚠️ This page may combine multiple inventors who share the name “GOEL MANISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOEL MANISH

TEXAS INSTRUMENTS INC

Signal field controller, method of controlling and MIMO transmitter employing the same

Computer and methods for solving math functions

Relay attack countermeasure system

Hybrid IMMSE-LMMSE receiver processing technique and apparatus for a MIMO WLAN

Apparatus and method for physically unclonable function (PUF) for a memory array

Apparatus for physically unclonable function (PUF) for a memory array

Calibrated-output analog-to-digital converter apparatus and methods

MIMO decoding

High speed decoder

Wireless access modem having downstream channel resynchronization method

Methods and apparatus to determine and apply polarity-based error correction code

Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file

Low energy accelerator processor architecture with short parallel instruction word

CRC-based forward error correction circuitry and method

Methods and apparatus to create a physically unclonable function

Scalable VLSI architecture for K-best breadth-first decoding

Wireless access modem having downstream channel resynchronization method

Method of slip compensation for integer frequency offset correction in a wireless communication system

Circuit for computing the absolute value of complex numbers

Radix-N architecture for deinterleaver-depuncturer block

Methods and apparatus to create a physically unclonable function

Methods and apparatus to determine and apply polarity-based error correction code

Low energy accelerator processor architecture with short parallel instruction word

Methods and apparatus to detect and correct errors in destructive read non-volatile memory

Semi-global stereo correspondence processing with lossless image decomposition

Apparatus and method of detection for a packet-based wireless receiver employing multiple, concurrent transmitted streams

Reconfigurable chip level equalizer architecture for multiple antenna systems

Method of synchronization for packet based, OFDM wireless systems with multiple receive chains

Circuit and method for imprint reduction in FRAM memories

SAMSUNG ELECTRONICS CO LTD

Method and apparatus for a wearable based authentication for improved user experience

System and method for 3D association of detected objects

Convolution streaming engine for deep neural networks

Foveated domain storage and processing

Method and electronic device for providing authentication using an image sensor

System and method for convolutional layer structure for neural networks

GOEL MANISH

Membrane-based hybrid process for separation of mixtures of organics, solids, and water

Extended bidirectional hamming code for double-error correction and triple-error detection

Memory with segmented error correction codes

Performing an iterative bundle adjustment for an imaging device

KIM HUN-SEOK

Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding

Receiver power saving via block code failure detection

LEE SEOK-JUN

High-speed add-compare-select (ACS) circuit

Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder

I3 NANOTEC LLC

Processing plant for performing membrane-based hybrid process for separation of mixtures of organics, solids, and water

SYNOPSYS INC

System and method for power verification using efficient merging of power state tables

DIRENZO MICHAEL T

Flexible and efficient memory utilization for high bandwidth receivers, integrated circuits, systems, methods and processes of manufacture

SUN YANG

Scalable decoder architecture for low density parity check codes

ATRENTA INC

Method for checking constraints equivalence of an integrated circuit design

GANGADHARAN SRIDHAR

Computer-aided design system and methods thereof for merging design constraint files across operational modes

ADVANI SIDDHARTH K

Performing a loop closure detection