Inventor
IRISH JOHN D
US27 patents
⚠️ This page may combine multiple inventors who share the name “IRISH JOHN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS6314491B1Nov 6, 2001
Peer-to-peer cache moves in a multiprocessor data processing system
IBM95 citations97
US5168571ADec 1, 1992
System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data
IBM161 citations95
US6000011ADec 7, 1999
Multi-entry fully associative transition cache
IBM29 citations89
US10761995B2Sep 1, 2020
Integrated circuit and data processing system having a configurable cache directory for an accelerator
IBM11 citations85
US9575825B2Feb 21, 2017
Push instruction for pushing a message payload from a sending thread to a receiving thread
IBM6 citations84
US9342387B1May 17, 2016
Hardware-assisted interthread push communication
IBM13 citations84
US9286148B1Mar 15, 2016
Hardware-assisted interthread push communication
IBM13 citations84
US7757040B2Jul 13, 2010
Memory command and address conversion between an XDR interface and a double data rate interface
IBM8 citations81
US6922753B2Jul 26, 2005
Cache prefetching
IBM7 citations74
US9766890B2Sep 19, 2017
Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread
IBM2 citations73
US9678812B2Jun 13, 2017
Addressing for inter-thread push communication
IBM2 citations73
US11113204B2Sep 7, 2021
Translation invalidation in a translation cache serving an accelerator
IBM1 citations72
US11030110B2Jun 8, 2021
Integrated circuit and data processing system supporting address aliasing in an accelerator
IBM0 citations62
US7721023B2May 18, 2010
I/O address translation method for specifying a relaxed ordering for I/O accesses
IBM2 citations62
US7716423B2May 11, 2010
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes
IBM5 citations62
US9778933B2Oct 3, 2017
Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread
IBM0 citations52
US9684551B2Jun 20, 2017
Addressing for inter-thread push communication
IBM1 citations52
US9569293B2Feb 14, 2017
Push instruction for pushing a message payload from a sending thread to a receiving thread
IBM0 citations52
US10846235B2Nov 24, 2020
Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
IBM0 citations51
US7089387B2Aug 8, 2006
Methods and apparatus for maintaining coherency in a multi-processor system
IBM1 citations49
US7539840B2May 26, 2009
Handling concurrent address translation cache misses and hits under those misses while maintaining command order
IBM1 citations47
US10613979B2Apr 7, 2020
Accelerator memory coherency with single state machine
IBM0 citations42
US10528399B2Jan 7, 2020
Techniques for faster loading of data for accelerators
IBM0 citations34