Inventor

KAO YA-CHEN

TW46 patents

⚠️ This page may combine multiple inventors who share the name “KAO YA-CHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAO YA-CHEN

TAIWAN SEMICONDUCTOR MFG CO LTD

HKMG high voltage CMOS for embedded non-volatile memory

Dual silicide formation method to embed split gate flash memory in high-k metal gate (HKMG) technology

HKMG high voltage CMOS for embedded non-volatile memory

Recessed salicide structure to integrate a flash memory device with a high κ, metal gate logic device

Method to improve floating gate uniformity for non-volatile memory devices

STI recess method to embed NVM memory in HKMG replacement gate technology

Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

Method for manufacturing semiconductor device including dummy gate electrodes

Memory device with metal gate

Semiconductor device with metal gate memory device and metal gate logic device and method for manufacturing the same

Semiconductor device and method for manufacturing the same

High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory

Integrated circuit structure and manufacturing method thereof

Cell-like floating-gate test structure

Cell-like floating-gate test structure

Integration of magneto-resistive random access memory and capacitor

High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory

Contactless communications using ferromagnetic material

Method for manufacturing semiconductor device with metal gate memory device and metal gate logic device

High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory

Integration of magneto-resistive random access memory and capacitor

Contact formation for split gate flash memory

Method to improve floating gate uniformity for non-volatile memory device

Cell-like floating-gate test structure

TAIWAN SEMICONDUCTOR MFG

MRAM device with continuous MTJ tunnel layers

Poly etching solution to improve silicon trench for low STI profile

Split-gate memory cells and fabrication methods thereof

Spin torque transfer magnetic tunnel junction structure

Split-gate memory cells and fabrication methods thereof

Flash memory cell with split gate structure and method for forming the same

Architecture to suppress bit-line leakage

Contact formation for split gate flash memory

Method of fabricating a magnetoresistive random access structure

KAO YA-CHEN

MRAM cell structure with a blocking layer for avoiding short circuits

Test structures, methods of manufacturing thereof, test methods, and MRAM arrays

CHIANG TIEN-WEI

Magnetoresistive random access memory

MRAM device and fabrication method thereof

AU OPTRONICS CORP

Display device with haze layer

Display device with rear light transmitting module

LIN CHUN-JUNG

Reverse connection MTJ cell for STT MRAM

CHEN CHIH-MING

Structure and method for a MRAM device with an oxygen absorbing cap layer

YANG PING-LIN

Contactless communications using ferromagnetic material

LIU MING-TE

Magnetoresistive random access memory and method of making the same

AUO CORP

Display device

WANG YU-JEN

Sacrifice layer structure and method for magnetic tunnel junction (MTJ) etching process

LAI CHIH-HUANG

Domain wall assisted spin torque transfer magnetresistive random access memory structure