Inventor

KAI JAMES

US120 patents

⚠️ This page may combine multiple inventors who share the name “KAI JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAI JAMES

SANDISK TECHNOLOGIES LLC

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Concurrent formation of memory openings and contact openings for a three-dimensional memory device

Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof

Three-dimensional memory device containing separately formed drain select transistors and method of making thereof

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Three-dimensional memory device containing a lateral source contact and method of making the same

Through-memory-level via structures for a three-dimensional memory device

Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof

Through-memory-level via structures for a three-dimensional memory device

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

Through-memory-level via structures for a three-dimensional memory device

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings

Concurrent formation of memory openings and contact openings for a three-dimensional memory device

Three-dimensional memory device containing floating gate select transistor

High voltage field effect transistor with laterally extended gate dielectric and method of making thereof

Three-dimensional memory device having drain select level isolation structure and method of making thereof

Grouping memory cells into sub-blocks for program speed uniformity

Within array replacement openings for a three-dimensional memory device

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same

Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes

Three-dimensional device with bonded structures including a support die and methods of making the same

SANDISK TECHNOLOGIES INC

Multi tier three-dimensional memory devices including vertically shared bit lines

Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks

Three dimensional NAND device with silicide containing floating gates

Ultrahigh density vertical NAND memory device and method of making thereof

Monolithic three-dimensional NAND strings and methods of fabrication thereof

Three dimensional NAND device with silicide containing floating gates and method of making thereof

Method of forming an active area with floating gate negative offset profile in FG NAND memory

Three dimensional vertical NAND device with floating gates

Select gate formation for nanodot flat cell

SANDISK CORP

Methods of forming integrated circuit devices using composite spacer structures

Methods of forming NAND flash memory with fixed charge

Composite charge storage structure formation in non-volatile memory using etch stop technologies

Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation

Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation

Methods of forming NAND memory with virtual channel

Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer

ALSMEIER JOHANN

Ultrahigh density vertical NAND memory device and method of making thereof

Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof

ADVANCED MICRO DEVICES INC

Method for forming dual inlaid structures for IC interconnections