Inventor
GILBERT JEFFREY D
US26 patents
⚠️ This page may combine multiple inventors who share the name “GILBERT JEFFREY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS6271100B1Aug 7, 2001
Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
IBM91 citations97
US6417070B1Jul 9, 2002
Method for forming a liner in a trench
IBM15 citations84
US6893948B2May 17, 2005
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
IBM8 citations73
US6670263B2Dec 30, 2003
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
IBM9 citations73
US6660664B1Dec 9, 2003
Structure and method for formation of a blocked silicide resistor
IBM9 citations72
US6580140B1Jun 17, 2003
Metal oxide temperature monitor
IBM6 citations72
US6822311B2Nov 23, 2004
DC or AC electric field assisted anneal
IBM3 citations60
US6339022B1Jan 15, 2002
Method of annealing copper metallurgy
IBM6 citations59
US7714366B2May 11, 2010
CMOS transistor with a polysilicon gate electrode having varying grain size
IBM0 citations51
US6759260B2Jul 6, 2004
Metal oxide temperature monitor
IBM0 citations50
US6552411B2Apr 22, 2003
DC or AC electric field assisted anneal
IBM0 citations50
INTEL CORP
11 patentsUS7555597B2Jun 30, 2009
Direct cache access in multiple core processors
INTEL CORP9 citations84
US7647476B2Jan 12, 2010
Common analog interface for multiple processor cores
INTEL CORP9 citations83
US7228387B2Jun 5, 2007
Apparatus and method for an adaptive multiple line prefetcher
INTEL CORP11 citations82
US7581068B2Aug 25, 2009
Exclusive ownership snoop filter
INTEL CORP7 citations73
US9501129B2Nov 22, 2016
Dynamically adjusting power of non-core processor circuitry including buffer circuitry
INTEL CORP4 citations71
US7689778B2Mar 30, 2010
Preventing system snoop and cross-snoop conflicts
INTEL CORP7 citations71
US7124229B2Oct 17, 2006
Method and apparatus for improved performance for priority agent requests when symmetric agent bus parking is enabled
INTEL CORP2 citations57
US7779188B2Aug 17, 2010
System and method to reduce memory latency in microprocessor systems connected with a bus
INTEL CORP3 citations55
US10078592B2Sep 18, 2018
Resolving multi-core shared cache access conflicts
INTEL CORP0 citations52
US8015365B2Sep 6, 2011
Reducing back invalidation transactions from a snoop filter
INTEL CORP1 citations52
US7484044B2Jan 27, 2009
Method and apparatus for joint cache coherency states in multi-interface caches
INTEL CORP1 citations52