Inventor

MESTAN BRIAN R

US26 patents

⚠️ This page may combine multiple inventors who share the name “MESTAN BRIAN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MESTAN BRIAN R

APPLE INC

Atomic operation predictor to predict if an atomic operation will successfully complete and a store queue to selectively forward data based on the predictor

Managing serial miss requests for load operations in a non-coherent memory system

Translation lookaside buffer invalidation by range

Reservation station with primary and secondary storage circuits for store operations

Processing memory accesses while supporting a zero size cache in a cache hierarchy

Atomic operation predictor to predict whether an atomic operation will complete successfully

Atomic operation predictor to predict whether an atomic operation will complete successfully

Reducing translation lookaside buffer searches for splintered pages

Cache replacement based on traversal tracking

Reducing translation lookaside buffer searches for splintered pages

Cache replacement based on traversal tracking

Limiting translation lookaside buffer searches using active page size

Translation lookaside buffer striping for efficient invalidation operations

Content-addressable memory filtering based on microarchitectural state

IBM

Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches

Hardware-assisted program trace collection with selectable call-signature capture

Buffering instructions of a single branch, backwards short loop within a virtual loop buffer

HALL RONALD

Efficiency of short loop instruction fetch

Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer

Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer

FRAZIER GILES R

Hardware performance-monitoring facility usage after context swaps

Task switch immunized performance monitoring

KONIGSBURG BRIAN R

Reducing store-hit-loads in an out-of-order processor

BURKY WILLIAM E

Processor and method for partially flushing a dispatched instruction group including a mispredicted branch

DOING RICHARD W

Tracking effective addresses in an out-of-order processor

QUALCOMM INC

Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process