Inventor

LEE CHUNG-JU

TW252 patents

⚠️ This page may combine multiple inventors who share the name “LEE CHUNG-JU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE CHUNG-JU

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of spacer patterning to form a target integrated circuit pattern

Method and structure for semiconductor mid-end-of-line (MEOL) process

Lithography using high selectivity spacers for pitch reduction

Method of fabricating semiconductor device with reduced trench distortions

Interconnect structure having an etch stop layer over conductive lines

Method and structure of cut end with self-aligned double patterning

Methods of forming interconnect structures in semiconductor fabrication

Self-aligned via structures with barrier layers

Structure and method for a low-k dielectric with pillar-type air-gaps

Magnetic tunnel junctions

Memory device and fabrication method thereof

Etch damage and ESL free dual damascene metal interconnect

Interconnect structure having an etch stop layer over conductive lines

Memory device and method for manufacturing the same

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Method and structure for semiconductor mid-end-of-line (MEOL) process

Lithography using high selectivity spacers for pitch reduction

Self-aligned double spacer patterning process

Via connection to a partially filled trench

Etch damage and ESL free dual damascene metal interconnect

Interconnect structure having an etch stop layer over conductive lines

Copper etching integration scheme

Integrated circuit interconnects and methods of making same

Method of double patterning lithography process using plurality of mandrels for integrated circuit applications

Integrated circuit interconnects and methods of making same

Additional etching to increase via contact area

Method of forming an interconnect structure for a semiconductor device

Material and process for copper barrier layer

Copper etching integration scheme

TAIWAN SEMICONDUCTOR MFG

Method for integrated circuit patterning

Spacer etching process for integrated circuit design

Structure and method for a low-K dielectric with pillar-type air-gaps

Lithography using high selectivity spacers for pitch reduction

Self-aligned double spacer patterning process

Semiconductor patterning

Interconnect structure and method of forming the same

Method for integrated circuit patterning

Self-aligned double spacer patterning process

Semiconductor device manufacturing methods

Semiconductor structure and semiconductor fabricating process for the same

Method of fabricating an air gap using a damascene process and structure of same

Copper etching integration scheme

VANGUARD INT SEMICONDUCT CORP

Method of forming shallow trench isolation structure

Shallow trench isolator via non-critical chemical mechanical polishing

Self-planarized shallow trench isolation

LEE CHUNG JU

Portable vaporizer

UNITED MICROELECTRONICS CORP

Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

SINGH SUNIL KUMAR

Etch damage and ESL free dual damascene metal interconnect

LAM RES CORP

Use of ammonia for etching organic low-k dielectrics

TAIWAN SEMINCONDUCTOR MFG COMPANY LTD

Method of fabricating an semiconductor interconnect structure