Inventor
MUKHERJEE RAJARSHI
IN25 patents
⚠️ This page may combine multiple inventors who share the name “MUKHERJEE RAJARSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
13 patentsUS11467851B1Oct 11, 2022
Machine learning (ML)-based static verification for derived hardware-design elements
SYNOPSYS INC3 citations72
US9529948B2Dec 27, 2016
Minimizing crossover paths for functional verification of a circuit description
SYNOPSYS INC5 citations70
US10831961B2Nov 10, 2020
Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result data
SYNOPSYS INC2 citations65
US9032339B2May 12, 2015
Ranking verification results for root cause analysis
SYNOPSYS INC3 citations59
US11403450B2Aug 2, 2022
Convergence centric coverage for clock domain crossing (CDC) jitter in simulation
SYNOPSYS INC0 citations56
US11222154B2Jan 11, 2022
State table complexity reduction in a hierarchical verification flow
SYNOPSYS INC0 citations56
US11288427B2Mar 29, 2022
Automated root-cause analysis, visualization, and debugging of static verification results
SYNOPSYS INC0 citations55
US12393754B2Aug 19, 2025
Generating a reduced block model view on-the-fly
SYNOPSYS INC0 citations51
US9792394B2Oct 17, 2017
Accurate glitch detection
SYNOPSYS INC1 citations46
US11907631B2Feb 20, 2024
Reset domain crossing detection and simulation
SYNOPSYS INC0 citations45
US10586001B2Mar 10, 2020
Automated root-cause analysis, visualization, and debugging of static verification results
SYNOPSYS INC0 citations45
US11556406B2Jan 17, 2023
Automatic root cause analysis of complex static violations by static information repository exploration
SYNOPSYS INC0 citations43
US9886753B2Feb 6, 2018
Verification of circuit structures including sub-structure variants
SYNOPSYS INC0 citations34
FUJITSU LTD
7 patentsUS6301687B1Oct 9, 2001
Method for verification of combinational circuits using a filtering oriented approach
FUJITSU LTD135 citations98
US5649165AJul 15, 1997
Topology-based computer-aided design system for digital circuits and method thereof
FUJITSU LTD88 citations96
US6532440B1Mar 11, 2003
Multiple error and fault diagnosis based on Xlists
FUJITSU LTD39 citations92
US6408424B1Jun 18, 2002
Verification of sequential circuits with same state encoding
FUJITSU LTD30 citations92
US7194710B2Mar 20, 2007
Scheduling events in a boolean satisfiability (SAT) solver
FUJITSU LTD13 citations84
US7383168B2Jun 3, 2008
Method and system for design verification and debugging of a complex computing system
FUJITSU LTD11 citations81
US7032192B2Apr 18, 2006
Performing latch mapping of sequential circuits
FUJITSU LTD15 citations81