Inventor

IWASAKI TOMOKO OGURA

US50 patents

⚠️ This page may combine multiple inventors who share the name “IWASAKI TOMOKO OGURA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IWASAKI TOMOKO OGURA

MICRON TECHNOLOGY INC

Memory devices with four data line bias levels

Sequential SLC read optimization

Managing sub-block erase operations in a memory sub-system

Vertical string driver for memory array

In-line programming adjustment of a memory cell in a memory sub-system

Key-value data storage system using content addressable memory

Performing error control operation on memory component for garbage collection

Garbage collection in a memory component using an adjusted parameter

Managing sub-block erase operations in a memory sub-system

Memory devices including heaters

Fast bit erase for upper tail tightening of threshold voltage distributions

Volatile data storage in NAND memory

In-line programming adjustment of a memory cell in a memory sub-system

Memory array structures and methods of forming memory array structures

Fast bit erase for upper tail tightening of threshold voltage distributions

Sequential SLC read optimization

Reducing maximum programming voltage in memory programming operations

Garbage collection in a memory sub-system during a low battery state

Responding to changes in available power supply

Memory array structures and methods for determination of resistive characteristics of access lines

Apparatus for rapid data destruction

Garbage collection in a memory sub-system during a low battery state

Garbage collection in a memory component using an adjusted parameter

Apparatus and methods for rapid data destruction

Responding to changes in available power supply

Apparatus for determining memory cell data states

Managing sub-block erase operations in a memory sub-system

Memory devices with four data line bias levels

Apparatus and methods for determining memory cell data states

Integrated assemblies having conductive-shield-structures between linear-conductive-structures

Integrated assemblies having conductive-shield-structures between linear-conductive-structures

Dynamic latches above a three-dimensional non-volatile memory array

Redundancy and majority voting in a key-value data storage system using content addressable memory

Memory devices including heaters

Double single level cell program in a memory device

Single-level cell program-verify, latch-limited data recovery

Health scan for content addressable memory

Ganged single level cell verify in a memory device

Overwrite mode in memory programming operations

Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device

All level coarse/fine programming of memory cells

Concurrent slow-fast memory cell programming

Programming content addressable memory

Key storage for sorted string tables using content addressable memory

Creating dynamic latches above a three-dimensional non-volatile memory array

Microelectronic devices, and related memory devices and electronic systems

Erase operation with electron injection for reduction of cell-to-cell interference in a memory sub-system

Memory devices with program verify levels based on compensation values

Cellular signal mesh network

OGURA SEIKI

High density vertical structure nitride flash memory