Inventor

KUO JIUN-MING

TW43 patents

⚠️ This page may combine multiple inventors who share the name “KUO JIUN-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUO JIUN-MING

TAIWAN SEMICONDUCTOR MFG CO LTD

Jog design in integrated circuits

Germanium hump reduction

Semiconductor device with a core-shell feature and method for forming the same

Dielectric isolation structure for multi-gate transistors

Fin field-effect transistor device and method

Fin field-effect transistor device and method

Fin field-effect transistor device and method

Semiconductor device and manufacturing method thereof

Methods of forming of inner spacer structure using semiconductor material with variable germanium concentration

Tapered dielectric layer for preventing electrical shorting between gate and back side via

Inner spacer structure and methods of forming such

Dielectric isolation structure for multi-gate transistors

Dielectric fin structure

Seal ring structures

Semiconductor device and methods of forming the same

Fin field-effect transistor device and method

Dielectric fin structure

Fin field-effect transistor device and method

Semiconductor structure and method for forming the same

Dielectric isolation structure for multi-gate transistors

Dielectric fin structure

Manufacturing method of semiconductor device

Fin loss prevention

Germanium hump reduction

Bent fin devices

Fin loss prevention

Semiconductor structure and related methods

Semiconductor structure and related methods

Formation method of semiconductor device with gate all around structure

Multigate device structure with engineered cladding and method making the same

Semiconductor devices and methods of forming the same

Jog design in integrated circuits

Multi-gate transistor channel height adjustment

Gate all around device and method of forming the same

Semiconductor device with varying gate dimensions and methods of forming the same

Mandrel structures and methods of fabricating the same in semiconductor devices

FinFET device and method of forming the same

FinFET having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins

Wavy profile mitigation

Silicon-germanium Fins and methods of processing the same in field-effect transistors

Integrated circuit structure and method for fabricating the same

Active region cut process

TAIWAN SEMICONDUCTOR MFG

Jog design in integrated circuits