Inventor

YI WANBING

SG78 patents

⚠️ This page may combine multiple inventors who share the name “YI WANBING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YI WANBING

GLOBALFOUNDRIES SG PTE LTD

Magnetic shielding of MRAM package

Integrated circuit with memory cells having reliable interconnection

High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same

Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application

Integrated magnetic random access memory with logic device

STT-MRAM flip-chip magnetic shielding and method for producing the same

Robust chamfer design for seal ring

Top electrode dome formation

Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same

Integrated inductor and magnetic random access memory device

Magnetic shielding for MTJ device or bit

Integrated magnetic random access memory with logic device having low-k interconnects

Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

Memory devices and methods of forming the same

MTJ bottom metal via in a memory cell and method for producing the same

Memory devices and methods of forming the same

MRAM chip magnetic shielding

Embedded MRAM in interconnects and method for producing the same

MRAM device with improved seal ring and method for producing the same

Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same

Magnetic tunnel junction stack alignment scheme

Planar passivation for pads

Integrated circuit structures with spin torque transfer magnetic random access memory ultilizing aluminum metallization layers and methods for fabricating the same

Magnetic memory device and method of forming thereof

Integrated two-terminal device with logic device for embedded application

Pillar contact extension and method for producing the same

Integrated magnetic random access memory with logic device having low-K interconnects

Integrated two-terminal device with logic device for embedded application

Integrated circuits with magnetic tunnel junction memory cells and methods for producing the same

Magnetism-controllable dummy structures in memory device

Non-volatile memory device with TSI/TSV application

Resistive memory device and methods of making such a resistive memory device

MRAM magnetic shielding with fan-out wafer level packaging

Integrated circuits with vertical capacitors and methods for producing the same

Integrated circuits with aluminum via structures and methods for fabricating the same

3D MRAM with through silicon vias or through silicon trenches magnetic shielding

Vertical and planar RRAM with tip electrodes and methods for producing the same

Galvanic isolation using isolation break between redistribution layer electrodes

Correlated electron resistive memory device and integration schemes

Memory cells and methods for forming memory cells

Memory devices and methods of forming memory devices

Memory devices and methods of forming the same

Memory devices and methods of forming memory devices

Self-aligned planarization of low-k dielectrics and method for producing the same

Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same

Memory device with density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology

Device with capping layer for improved residue defect and method of production thereof

Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures

Self-aligned planarization of low-K dielectrics and method for producing the same

GLOBALFOUNDRIES INC

Chamfering for stress reduction on passivation layer