Inventor
SURENDRA MAHESWARAN
US41 patents
⚠️ This page may combine multiple inventors who share the name “SURENDRA MAHESWARAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
33 patentsUS6864041B2Mar 8, 2005
Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
IBM538 citations98
US7361991B2Apr 22, 2008
Closed air gap interconnect structure
IBM67 citations97
US7350186B2Mar 25, 2008
Methods and apparatus for managing computing deployment in presence of variable workload
IBM146 citations97
US6442445B1Aug 27, 2002
User configurable multivariate time series reduction tool control method
IBM94 citations96
US6518136B2Feb 11, 2003
Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication
IBM42 citations95
US6678569B2Jan 13, 2004
User configurable multivariate time series reduction tool control method
IBM66 citations94
US7822785B2Oct 26, 2010
Methods and apparatus for composite configuration item management in configuration management database
IBM24 citations92
US7393776B2Jul 1, 2008
Method of forming closed air gap interconnects and structures formed thereby
IBM26 citations92
US7309649B2Dec 18, 2007
Method of forming closed air gap interconnects and structures formed thereby
IBM33 citations92
US7056782B2Jun 6, 2006
CMOS silicide metal gate integration
IBM25 citations92
US6936522B2Aug 30, 2005
Selective silicon-on-insulator isolation structure and method
IBM37 citations92
US6869899B2Mar 22, 2005
Lateral-only photoresist trimming for sub-80 nm gate stack
IBM26 citations92
US6732908B2May 11, 2004
High density raised stud microjoining system and methods of fabricating the same
IBM19 citations92
US7039559B2May 2, 2006
Methods and apparatus for performing adaptive and robust prediction
IBM39 citations91
US6584368B2Jun 24, 2003
User configurable multivariate time series reduction tool control method
IBM36 citations91
US6365326B1Apr 2, 2002
Pattern density tailoring for etching of advanced lithographic mask
IBM19 citations90
US6528363B2Mar 4, 2003
Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
IBM22 citations89
US7346401B2Mar 18, 2008
Systems and methods for providing constrained optimization using adaptive regulatory control
IBM14 citations82
US6521383B2Feb 18, 2003
Pattern density tailoring for etching of advanced lithographic masks
IBM15 citations82
US7913227B2Mar 22, 2011
Methods and apparatus for management of configuration item lifecycle state transitions
IBM17 citations79
US7326983B2Feb 5, 2008
Selective silicon-on-insulator isolation structure and method
IBM8 citations73
US6743686B2Jun 1, 2004
Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication
IBM8 citations73
US8347289B2Jan 1, 2013
Method and apparatus for online sample interval determination
IBM4 citations63
US7987146B2Jul 26, 2011
System and method for matching multi-node software system provisioning requirements and capabilities using rough set theory
IBM6 citations63
US7923786B2Apr 12, 2011
Selective silicon-on-insulator isolation structure and method
IBM3 citations62
US7716016B2May 11, 2010
Method and apparatus for automatic uncertainty-based management feedback controller
IBM3 citations62
US7953729B2May 31, 2011
Resource optimizations in computing utilities
IBM4 citations61
US7707345B2Apr 27, 2010
Methods and apparatus for managing deadtime in feedback control queuing system
IBM6 citations61
US7565655B2Jul 21, 2009
Methods and systems for control discovery in computing systems
IBM2 citations61
US7496564B2Feb 24, 2009
Resource optimizations in computing utilities
IBM2 citations61
US9577951B2Feb 21, 2017
Orchestrated peer-to-peer server provisioning
IBM1 citations52
US9195558B2Nov 24, 2015
Piloting in service delivery
IBM0 citations44
US7243169B2Jul 10, 2007
Method, system and program for oscillation control of an internal process of a computer program
IBM0 citations39