Inventor

PAONE PHIL C

US69 patents

⚠️ This page may combine multiple inventors who share the name “PAONE PHIL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAONE PHIL C

IBM

Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable

Changing chip function based on fuse states

Changing chip function based on fuse states

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low bower circuitry

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low power circuitry

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable

Non volatile memory RAD-hard (NVM-rh) system

Cognitive analysis using applied analog circuits

Method for low power operation and test using DRAM device

Generating a unique die identifier for an electronic chip

Implementing eFuse visual security of stored data using EDRAM

Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Implementing eFuse visual security of stored data using EDRAM

Structure for metal oxide semiconductor capacitor

Precision IC resistor fabrication

Electronic fuse cell and array

Optimizing data approximation analysis using low power circuitry

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Method of implementing buried FET below and beside FinFET on bulk substrate

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Semiconductor chip with power gating through silicon vias

Implementing semiconductor soc with metal via gate node high performance stacked transistors

Real time cognitive reasoning using a circuit with varying confidence level alerts

Real time cognitive reasoning using a circuit with varying confidence level alerts

Sensing circuit for a non-volatile memory cell having two complementary memory transistors

Electrically programmable fuse sense circuit

Cognitive analysis using applied analog circuits

Real time cognitive monitoring of correlations between variables

Real time cognitive monitoring of correlations between variables

Generating a unique die identifier for an electronic chip

Implementing eFuse visual security of stored data using EDRAM

System for testing charge trap memory cells

Implementing hidden security key in eFuses

Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

System for testing charge trap memory cells

ERICKSON KARL R

eDRAM having dynamic retention and performance tradeoff

FinFET with body contact

Independently voltage controlled volume of silicon on a silicon on insulator chip

Vertically stacked FETs with series bipolar junction transistor

Implementing semiconductor SoC with metal via gate node high performance stacked transistors

Plural differential pair employing FinFET structure

Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit

Deep trench embedded gate transistor

PAONE PHIL C

Soft error detection