Inventor

LIN FENG

CN339 patents

⚠️ This page may combine multiple inventors who share the name “LIN FENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN FENG

MICRON TECHNOLOGY INC

Digital dual-loop DLL design using coarse and fine loops

Methods and apparatus for duty cycle control

Capture clock generator using master and slave delay locked loops

Method and system for delay control in synchronization circuits

System and method to improve the efficiency of synchronous mirror delays and delay locked loops

Digital dual-loop DLL design using coarse and fine loops

Method and apparatus for setting and compensating read latency in a high speed DRAM

Method and apparatus for improving stability and lock time for synchronous circuits

Delay-lock loop and method adapting itself to operate over a wide frequency range

Phase splitter using digital delay locked loops

Interleaved delay line for phase locked and delay locked loops

System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines

System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal

Phase detector for all-digital phase locked and delay locked loops

System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal

System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal

Output impedance calibration for signaling

Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay

Phase detector for reducing noise

Phase detector for reducing noise

Method and apparatus for calibrating driver impedance

Phase detector and method providing rapid locking of delay-lock loops

Bias generator with feedback control

Method and apparatus to set a tuning range for an analog delay

Memory system and method for strobing data, command and address signals

Memory system and method for strobing data, command and address signals

Memory system and method for strobing data, command and address signals

Skew tolerant high-speed digital phase detector

Method and apparatus to set a tuning range for an analog delay

Phase detector for reducing noise

Phase detector for reducing noise

Memory system and method for strobing data, command and address signals

Phase detector for reducing noise

Interleaved delay line for phase locked and delay locked loops

Circuits and methods of temperature compensation for refresh oscillator

Phase detector for all-digital phase locked and delay locked loops

Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM

Methods and apparatus for delay circuit

Interleaved delay line for phase locked and delay locked loops

System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines

YAN TIESHENG

Circuits and methods for driving LED light sources

Circuits and methods for driving light sources

Circuits and methods for driving light sources

O2MICRO INC

Circuits and methods for driving light sources

Circuits and methods for driving light sources

NETPOWER TECHNOLOGIES INC

Soft start for a synchronous rectifier in a power converter

Plural power converters with individual conditioned error signals shared on a current sharing bus

MCNEIL PPC INC

Ibuprofen composition

(unassigned)

Packet-switched facsimile network and method of operation

ALIBABA GROUP HOLDING LTD

Three-dimensional graphical user interface for informational input in virtual reality environment