Inventor

KAPUR ROHIT

US42 patents

⚠️ This page may combine multiple inventors who share the name “KAPUR ROHIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAPUR ROHIT

SYNOPSYS INC

Dynamic scan chains and test pattern generation methodologies therefor

Method and system for controlling test data volume in deterministic test pattern generation

Deterministic bist architecture including MISR filter

System and method for time slicing deterministic patterns for reseeding in logic built-in self-test

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

System and method for automatically retargeting test vectors between different tester types

System and method for high-level test planning for layout

Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation

Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation

System and method for high-level test planning for layout

Method for placement-based scan-in and scan-out ports selection

Slack-based transition-fault testing

Method and apparatus for limiting power dissipation in test

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

Scan compression circuit and method of design therefor

Slack-based transition-fault testing

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

Command coverage analyzer

Dynamically reconfigurable shared scan-in test architecture

Test design optimizer for configurable scan architectures

Layout-aware test pattern generation and fault detection

Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits

Scheme for masking output of scan chains in test circuit

Scheme for masking output of scan chains in test circuit

Automatically generated schematics and visualization

Command coverage analyzer

Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment

Scheme for masking output of scan chains in test circuit

Hierarchical testing architecture using core circuit with pseudo-interfaces

Identifying failure indicating scan test cells of a circuit-under-test

Reordering or removal of test patterns for detecting faults in integrated circuit

Localizing fault flop in circuit by using modified test pattern

KAPUR ROHIT

Implementing hierarchical design-for-test logic for modular circuit design

Test design optimizer for configurable scan architectures

Systemic diagnostics for increasing wafer yield

CHANDRA ANSHUMAN

Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry

IBM

Hybrid partial scan method

KUMAR ASHWIN

Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimization

SANYAL ALODEEP

Layout-aware test pattern generation and fault detection