Inventor
BHARADWAJ JAYASHANKAR
US20 patents
⚠️ This page may combine multiple inventors who share the name “BHARADWAJ JAYASHANKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
14 patentsUS5894576AApr 13, 1999
Method and apparatus for instruction scheduling to reduce negative effects of compensation code
INTEL CORP44 citations92
US5787287AJul 28, 1998
Representation of control flow and data dependence for machine
INTEL CORP27 citations92
US6675380B1Jan 6, 2004
Path speculating instruction scheduler
INTEL CORP34 citations89
US9244677B2Jan 26, 2016
Loop vectorization methods and apparatus
INTEL CORP9 citations84
US7240342B1Jul 3, 2007
User transparent continuous compilation
INTEL CORP18 citations80
US9898266B2Feb 20, 2018
Loop vectorization methods and apparatus
INTEL CORP3 citations73
US10402177B2Sep 3, 2019
Methods and systems to vectorize scalar computer program loops having loop-carried dependences
INTEL CORP2 citations72
US9921832B2Mar 20, 2018
Instruction to reduce elements in a vector register with strided access pattern
INTEL CORP4 citations72
US9733913B2Aug 15, 2017
Methods and systems to vectorize scalar computer program loops having loop-carried dependences
INTEL CORP3 citations72
US9268541B2Feb 23, 2016
Methods and systems to vectorize scalar computer program loops having loop-carried dependences
INTEL CORP4 citations72
US7512930B2Mar 31, 2009
Program object read barrier
INTEL CORP2 citations63
US7487336B2Feb 3, 2009
Method for register allocation during instruction scheduling
INTEL CORP4 citations63
US10372450B2Aug 6, 2019
Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
INTEL CORP0 citations51
US9891920B2Feb 13, 2018
Systems, apparatuses, and methods for generating a dependency vector based on two source writemask registers
INTEL CORP0 citations51
BHARADWAJ JAYASHANKAR
4 patentsUS9798541B2Oct 24, 2017
Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register
BHARADWAJ JAYASHANKAR4 citations71
US9354881B2May 31, 2016
Systems, apparatuses, and methods for generating a dependency vector based on two source writemask registers
BHARADWAJ JAYASHANKAR0 citations50
US9189236B2Nov 17, 2015
Speculative non-faulting loads and gathers
BHARADWAJ JAYASHANKAR0 citations50
US9268626B2Feb 23, 2016
Apparatus and method for vectorization with speculation support
BHARADWAJ JAYASHANKAR0 citations36