Inventor

TSUKIKAWA YASUHIKO

JP41 patents

⚠️ This page may combine multiple inventors who share the name “TSUKIKAWA YASUHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSUKIKAWA YASUHIKO

MITSUBISHI ELECTRIC CORP

Semiconductor memory device having a redundant row and a redundant column which can be accessed prior to substitution

Charge pump circuit having an improved charge pumping efficiency

Synchronous semiconductor device having circuitry capable of surely resetting test mode

Substrate potential generation circuit that can suppress variation of output voltage with respect to change in external power supply voltage and environment temperature

Delay circuit having delay time free from influence of operation environment

Semiconductor memory device capable of executing earlier command operation in test mode

Semiconductor memory device having test mode

Semiconductor memory device having storage capacity of 22N+1 bits

Semiconductor memory device clamping the overshoot and undershoot of input signal by circuit with PN junction

Complementary differential amplifier in which direct current amplification gain can be set arbitrarily and semiconductor memory divice using the same

Semiconductor memory device capable of switching output data width

Semiconductor memory device capable of reducing power supply voltage in a DRAM&#39;s word driver

Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit

Semiconductor memory device permitting large output current from output buffer

Semiconductor memory device with reduced output noise

Semiconductor memory device suitable for high integration

Semiconductor memory device with test mode decision circuit

Semiconductor memory device comprising address transition detecting circuit having stable response characteristic for address signal conversion

Dynamic semiconductor memory device that can control through current of input buffer circuit for external input/output control signal

Semiconductor memory device having test mode

Semiconductor memory device having layout area of periphery of output pad reduced

Semiconductor memory device provided with I/O clamp circuit

Semiconductor memory device and test method therefor

Integrated semiconductor device

Multi-valued logical circuit with less latch-up

RENESAS TECH CORP

Semiconductor memory device having twin-cell units

Semiconductor memory device driven with low voltage

Semiconductor memory device with memory cells arranged in high density

Semiconductor device and level conversion circuit

Semiconductor memory circuit having normal operation mode and burn-in test mode

Configuration for generating a clock including a delay circuit and method thereof

Semiconductor memory device capable of switching output data width

Semiconductor memory device having dummy word line

Semiconductor device and level conversion circuit

Semiconductor memory device having nonvolatile memory cell of high operating stability

Semiconductor memory device with shortened connection length among memory block, data buffer and data bus

Semiconductor device with reduced terminal input capacitance

ZENTEL JAPAN CORP

Semiconductor memory device

Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Method and apparatus for writing oxide film

MITSUBISHI DENKI KABISHIKI KAI

Semiconductor memory device with write driver reset function

Semiconductor memory device capable of reducing power supply voltage in a DRAM's word driver