Inventor
CHAPPELL TERRY IVAN
US7 patents
Patents
7 patentsUS5920486AJul 6, 1999
Parameterized cells for generating dense layouts of VLSI circuits
IBM150 citations95
US6131182AOct 10, 2000
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
IBM72 citations92
US5973529AOct 26, 1999
Pulse-to-static conversion latch with a self-timed control circuit
IBM47 citations92
US5926487AJul 20, 1999
High performance registers for pulsed logic
IBM31 citations88
US5748012AMay 5, 1998
Methodology to test pulsed logic circuits in pseudo-static mode
IBM23 citations88
US6005416ADec 21, 1999
Compiled self-resetting CMOS logic array macros
IBM10 citations70
US6279024B1Aug 21, 2001
High performance, low power incrementer for dynamic circuits
IBM2 citations59