Inventor
DITLOW GARY S
US19 patents
⚠️ This page may combine multiple inventors who share the name “DITLOW GARY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS6383847B1May 7, 2002
Partitioned mask layout
IBM35 citations92
US6131182AOct 10, 2000
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros
IBM72 citations92
US6868374B1Mar 15, 2005
Method of power distribution analysis for I/O circuits in ASIC designs
IBM37 citations91
US6788302B1Sep 7, 2004
Partitioning and load balancing graphical shape data for parallel applications
IBM35 citations91
US7051307B2May 23, 2006
Autonomic graphical partitioning
IBM17 citations83
US5495188AFeb 27, 1996
Pulsed static CMOS circuit
IBM12 citations74
US9733630B2Aug 15, 2017
Interactive energy device for environmental stewardship
IBM4 citations73
US6301690B1Oct 9, 2001
Method to improve integrated circuit defect limited yield
IBM11 citations72
US6601025B1Jul 29, 2003
Method to partition the physical design of an integrated circuit for electrical simulation
IBM9 citations71
US6005416ADec 21, 1999
Compiled self-resetting CMOS logic array macros
IBM10 citations70
US8054662B2Nov 8, 2011
Content addressable memory array
IBM3 citations63
US7948782B2May 24, 2011
Content addressable memory reference clock
IBM5 citations63
US7552412B2Jun 23, 2009
Integrated circuit (IC) chip design method, program product and system
IBM2 citations62
US7679402B2Mar 16, 2010
Methods and apparatus for monitoring power gating circuitry and for controlling circuit operations in dependence on monitored power gating conditions
IBM2 citations57
US9599973B2Mar 21, 2017
Interactive energy device for environmental stewardship
IBM0 citations52
US10218300B2Feb 26, 2019
Transformer phase permutation causing more uniform transformer phase aging and general switching network suitable for same
IBM0 citations41