Inventor
SIVAKUMAR SAM
US14 patents
Patents
14 patentsUS6365529B1Apr 2, 2002
Method for patterning dual damascene interconnects using a sacrificial light absorbing material
INTEL CORP121 citations98
US6329118B1Dec 11, 2001
Method for patterning dual damascene interconnects using a sacrificial light absorbing material
INTEL CORP107 citations97
US6037255AMar 14, 2000
Method for making integrated circuit having polymer interlayer dielectric
INTEL CORP55 citations95
US6406995B1Jun 18, 2002
Pattern-sensitive deposition for damascene processing
INTEL CORP72 citations92
US6350670B1Feb 26, 2002
Method for making a semiconductor device having a carbon doped oxide insulating layer
INTEL CORP49 citations92
US6384481B1May 7, 2002
Single step electroplating process for interconnect via fill and metal line patterning
INTEL CORP33 citations91
US6020266AFeb 1, 2000
Single step electroplating process for interconnect via fill and metal line patterning
INTEL CORP33 citations91
US6649515B2Nov 18, 2003
Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
INTEL CORP35 citations89
US7648803B2Jan 19, 2010
Diagonal corner-to-corner sub-resolution assist features for photolithography
INTEL CORP10 citations82
US7374865B2May 20, 2008
Methods to pattern contacts using chromeless phase shift masks
INTEL CORP9 citations82
US7056645B2Jun 6, 2006
Use of chromeless phase shift features to pattern large area line/space geometries
INTEL CORP12 citations82
US6774037B2Aug 10, 2004
Method integrating polymeric interlayer dielectric in integrated circuits
INTEL CORP18 citations80
US7179570B2Feb 20, 2007
Chromeless phase shift lithography (CPL) masks having features to pattern large area line/space geometries
INTEL CORP5 citations72
US11569231B2Jan 31, 2023
Non-planar transistors with channel regions having varying widths
INTEL CORP3 citations69