Inventor
RAJAGOPALAN SARATHY
US10 patents
⚠️ This page may combine multiple inventors who share the name “RAJAGOPALAN SARATHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
9 patentsUS6586825B1Jul 1, 2003
Dual chip in package with a wire bonded die mounted to a substrate
LSI LOGIC CORP23 citations92
US6518161B1Feb 11, 2003
Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die
LSI LOGIC CORP26 citations92
US6441499B1Aug 27, 2002
Thin form factor flip chip ball grid array
LSI LOGIC CORP33 citations92
US6320127B1Nov 20, 2001
Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
LSI LOGIC CORP21 citations92
US6825556B2Nov 30, 2004
Integrated circuit package design with non-orthogonal die cut out
LSI LOGIC CORP21 citations89
US7041516B2May 9, 2006
Multi chip module assembly
LSI LOGIC CORP7 citations73
US6962437B1Nov 8, 2005
Method and apparatus for thermal profiling of flip-chip packages
LSI LOGIC CORP7 citations73
US7352062B2Apr 1, 2008
Integrated circuit package design
LSI LOGIC CORP6 citations70
US6465338B1Oct 15, 2002
Method of planarizing die solder balls by employing a die's weight
LSI LOGIC CORP1 citations51