Inventor
RANGANATHAN RAMASWAMY
US23 patents
⚠️ This page may combine multiple inventors who share the name “RANGANATHAN RAMASWAMY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
16 patentsUS6020221AFeb 1, 2000
Process for manufacturing a semiconductor device having a stiffener member
LSI LOGIC CORP128 citations95
US6798035B1Sep 28, 2004
Bonding pad for low k dielectric
LSI LOGIC CORP20 citations92
US6329278B1Dec 11, 2001
Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads
LSI LOGIC CORP40 citations90
US6963138B2Nov 8, 2005
Dielectric stack
LSI LOGIC CORP15 citations84
US6743979B1Jun 1, 2004
Bonding pad isolation
LSI LOGIC CORP16 citations84
US6825563B1Nov 30, 2004
Slotted bonding pad
LSI LOGIC CORP17 citations82
US6573113B1Jun 3, 2003
Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads
LSI LOGIC CORP13 citations79
US6266249B1Jul 24, 2001
Semiconductor flip chip ball grid array package
LSI LOGIC CORP8 citations74
US6670214B1Dec 30, 2003
Insulated bonding wire for microelectronic packaging
LSI LOGIC CORP9 citations72
US7205673B1Apr 17, 2007
Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing
LSI LOGIC CORP7 citations71
US6998638B2Feb 14, 2006
Test structure for detecting bonding-induced cracks
LSI LOGIC CORP2 citations62
US6781150B2Aug 24, 2004
Test structure for detecting bonding-induced cracks
LSI LOGIC CORP4 citations62
US6861748B2Mar 1, 2005
Test structure
LSI LOGIC CORP2 citations60
US6991147B2Jan 31, 2006
Insulated bonding wire tool for microelectronic packaging
LSI LOGIC CORP0 citations50
US6486002B1Nov 26, 2002
Tape design to reduce warpage
LSI LOGIC CORP1 citations49
US6425179B1Jul 30, 2002
Method for assembling tape ball grid arrays
LSI LOGIC CORP0 citations42