Inventor
KLAIBER ALEXANDER
US34 patents
⚠️ This page may combine multiple inventors who share the name “KLAIBER ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TRANSMETA CORP
8 patentsUS7380096B1May 27, 2008
System and method for identifying TLB entries associated with a physical address of a specified range
TRANSMETA CORP62 citations98
US7149872B2Dec 12, 2006
System and method for identifying TLB entries associated with a physical address of a specified range
TRANSMETA CORP70 citations98
US7310723B1Dec 18, 2007
Methods and systems employing a flag for deferring exception handling to a commit or rollback point
TRANSMETA CORP23 citations93
US7380098B1May 27, 2008
Method and system for caching attribute data for matching attributes with physical addresses
TRANSMETA CORP15 citations92
US7225299B1May 29, 2007
Supporting speculative modification in a data cache
TRANSMETA CORP22 citations92
US7149851B1Dec 12, 2006
Method and system for conservatively managing store capacity available to a processor issuing stores
TRANSMETA CORP19 citations92
US7089397B1Aug 8, 2006
Method and system for caching attribute data for matching attributes with physical addresses
TRANSMETA CORP16 citations92
US7478226B1Jan 13, 2009
Processing bypass directory tracking system and method
TRANSMETA CORP9 citations84
ROZAS GUILLERMO
6 patentsUS8239656B2Aug 7, 2012
System and method for identifying TLB entries associated with a physical address of a specified range
ROZAS GUILLERMO56 citations98
US7913058B2Mar 22, 2011
System and method for identifying TLB entries associated with a physical address of a specified range
ROZAS GUILLERMO58 citations98
US7873793B1Jan 18, 2011
Supporting speculative modification in a data cache
ROZAS GUILLERMO24 citations92
US7606979B1Oct 20, 2009
Method and system for conservatively managing store capacity available to a processor issuing stores
ROZAS GUILLERMO17 citations92
US7606997B1Oct 20, 2009
Method and system for using one or more address bits and an instruction to increase an instruction set
ROZAS GUILLERMO0 citations51
US7725656B1May 25, 2010
Braided set associative caching techniques
ROZAS GUILLERMO0 citations38
NVIDIA CORP
6 patentsUS9547602B2Jan 17, 2017
Translation lookaside buffer entry systems and methods
NVIDIA CORP7 citations83
US9632976B2Apr 25, 2017
Lazy runahead operation for a microprocessor
NVIDIA CORP5 citations82
US10108424B2Oct 23, 2018
Profiling code portions to generate translations
NVIDIA CORP2 citations71
US9891972B2Feb 13, 2018
Lazy runahead operation for a microprocessor
NVIDIA CORP0 citations50
US9823931B2Nov 21, 2017
Queued instruction re-dispatch after runahead
NVIDIA CORP0 citations50
US9740553B2Aug 22, 2017
Managing potentially invalid results during runahead
NVIDIA CORP0 citations50
KLAIBER ALEXANDER
3 patentsUS7937566B1May 3, 2011
Processing bypass directory tracking system and method
KLAIBER ALEXANDER3 citations61
US9652244B2May 16, 2017
Processing bypass directory tracking system and method
KLAIBER ALEXANDER0 citations50
US8209518B2Jun 26, 2012
Processing bypass directory tracking system and method
KLAIBER ALEXANDER0 citations50
ROZAS GUILLERMO J
2 patentsVMWARE INC
2 patentsUS10394560B2Aug 27, 2019
Efficient recording and replaying of non-deterministic instructions in a virtual machine and CPU therefor
VMWARE INC1 citations73
US9436471B2Sep 6, 2016
Efficient recording and replaying of non-deterministic instructions in a virtual machine and CPU therefor
VMWARE INC3 citations73
ANVIN H PETER
2 patentsINTELLECTUAL VENTURE FUNDING LLC
2 patentsUS8566564B2Oct 22, 2013
Method and system for caching attribute data for matching attributes with physical addresses
INTELLECTUAL VENTURE FUNDING LLC1 citations62
US8924648B1Dec 30, 2014
Method and system for caching attribute data for matching attributes with physical addresses
INTELLECTUAL VENTURE FUNDING LLC0 citations51