Inventor
GALATENKO ALEXEI V
RU12 patents
⚠️ This page may combine multiple inventors who share the name “GALATENKO ALEXEI V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI CORP
6 patentsUS7398486B2Jul 8, 2008
Method and apparatus for performing logical transformations for global routing
LSI CORP4 citations62
US7496870B2Feb 24, 2009
Method of selecting cells in logic restructuring
LSI CORP3 citations61
US7257791B2Aug 14, 2007
Multiple buffer insertion in global routing
LSI CORP3 citations61
US7401313B2Jul 15, 2008
Method and apparatus for controlling congestion during integrated circuit design resynthesis
LSI CORP4 citations60
US7568175B2Jul 28, 2009
Ramptime propagation on designs with cycles
LSI CORP0 citations48
US7246336B2Jul 17, 2007
Ramptime propagation on designs with cycles
LSI CORP0 citations48
LSI LOGIC CORP
4 patentsUS7103865B2Sep 5, 2006
Process and apparatus for placement of megacells in ICs design
LSI LOGIC CORP4 citations62
US7003739B2Feb 21, 2006
Method and apparatus for finding optimal unification substitution for formulas in technology library
LSI LOGIC CORP2 citations62
US7146591B2Dec 5, 2006
Method of selecting cells in logic restructuring
LSI LOGIC CORP1 citations50
US7111267B2Sep 19, 2006
Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths
LSI LOGIC CORP0 citations50