Inventor

KUMAR KAUSHIK A

US34 patents

⚠️ This page may combine multiple inventors who share the name “KUMAR KAUSHIK A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUMAR KAUSHIK A

IBM

Dual damascene integration of ultra low dielectric constant porous materials

Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention

Self-aligned patterned etch stop layers for semiconductor devices

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same

Structure and method for hybrid tungsten copper metal contact

Method for dual damascene integration of ultra low dielectric constant porous materials

Method for reactive ion etch processing of a dual damascene structure

De-fluorination of wafer surface and related structure

Dual damascene integration of ultra low dielectric constant porous materials

Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same

MOSFET with high angle sidewall gate and contacts for reduced miller capacitance

Polycarbosilane buried etch stops in interconnect structures

Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits

Method for fabricating a semiconductor structure

Polycarbosilane buried etch stops in interconnect structures

Method for forming conductive structures

Liner protection in deep trench etching

Stress relaxation, selective nitride phase removal

On-chip cooling systems for integrated circuits

Polycarbosilane buried etch stops in interconnect structures

Sidewall semiconductor transistors

Back end interconnect with a shaped interface

Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices

Sidewall semiconductor transistors

Metal interconnect and IC chip including metal interconnect

Metal interconnect forming methods and IC chip including metal interconnect

Thermal gradient control of high aspect ratio etching and deposition processes

INFINEON TECHNOLOGIES AG

Back end interconnect with a shaped interface

Crystallographic modification of hard mask properties

TOKYO ELECTRON LTD

Etch process for reducing directed self assembly pattern defectivity using direct current positioning

Method for bottom-up deposition of a film in a recessed feature

KUMAR KAUSHIK A

On-chip cooling for integrated circuits

On-chip cooling systems for integrated circuits

GAYLORD RICHARD H

Combined silicon oxide etch and contamination removal process