Inventor

INDUKURU VENKAT R

US30 patents

⚠️ This page may combine multiple inventors who share the name “INDUKURU VENKAT R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INDUKURU VENKAT R

IBM

Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information

Reallocating unused memory databus utilization to another processor when utilization is below a threshold

Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information

Method and apparatus for evaluating integrated circuit design performance using basic block vectors, cycles per instruction (CPI) information and microarchitecture dependent information

Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes

Continuous in-memory accumulation of hardware performance counter data

Identifying load-hit-store conflicts

Dynamic detection and software correction of incorrect lock and atomic update hint bits

Bidirectional counting of dual outcome events

Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes

System-wide topology and performance monitoring GUI tool with per-partition views

Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes

Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall

Bidirectional counting of dual outcome events

Monitoring software performance

Dynamic detection and correction of incorrect lock and atomic update hint bits

System-wide topology and performance monitoring GUI tool with per-partition views

BELL JR ROBERT H

Workload performance projection via surrogate program analysis for future information handling systems

Scaling instruction intervals to identify collection points for representative instruction traces

Workload performance projection for future information handling systems using microarchitecture dependent data

FRAZIER GILES R

Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register

Floating-point event counters with automatic prescaling

Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register

INDUKURU VENKAT R

Prioritizing instructions based on the number of delay cycles

Identifying load-hit-store conflicts

Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall

DESOTA DONALD R

Memory databus utilization management system and computer program product

BOSTIC WILLIAM A

System-wide topology and performance monitoring GUI tool with per-partition views

APPLE INC

Shader profiler

DOOLEY MILES R

Ineffective prefetch determination and latency optimization