Inventor

ALPERT CHARLES J

US47 patents

⚠️ This page may combine multiple inventors who share the name “ALPERT CHARLES J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALPERT CHARLES J

IBM

Clock aware placement

Latch placement for high performance and low power circuits

Analytical constraint generation for cut-based global placement

Fault-tolerant power-driven synthesis

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Computer-based modeling of integrated circuit congestion and wire distribution for products and services

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors

Constrained detailed placement

Automatic generation of wire tag lists for a metal stack

Automatic generation of wire tag lists for a metal stack

Resolving global coupling timing and slew violations for buffer-dominated designs

Clock power minimization with regular physical placement of clock repeater components

Legalization of VLSI circuit placement with blockages using hierarchical row slicing

Incremental timing-driven, physical-synthesis using discrete optimization

Buffer insertion to reduce wirelength in VLSI circuits

Boundary latch and logic placement to satisfy timing constraints

Post-placement cell shifting

Slew constrained minimum cost buffering

Concurrent buffering and layer assignment in integrated circuit layout

Power-driven synthesis under latency constraints

Routing centric design closure

Addressing coupled noise-based violations with buffering in a batch environment

Detailed routability by cell placement

Power driven synaptic network synthesis

Fault-tolerant power-driven synthesis

Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model

Slew constrained minimum cost buffering

Computer-based modeling of integrated circuit congestion and wire distribution for products and services

Incremental timing optimization and placement

Optimal timing-driven cloning under linear delay model

Efficient Ceff model for gate output slew computation in early synthesis

Techniques for parallel buffer insertion

ALPERT CHARLES J

Placement of structured nets

Clock optimization with local clock buffer control optimization

Datapath placement using tiered assignment

Consideration of local routing and pin access during VLSI global routing

Local objective optimization in global placement of an integrated circuit design

Post-placement cell shifting

Evaluating routing congestion based on average global edge congestion histograms

Accuracy pin-slew mode for gate delay calculation

Routability using multiplexer structures

System and computer program product for diffusion based cell placement migration

Method for diffusion based cell placement migration

Element placement in circuit design based on preferred location

Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design

Electronic design automation object placement with partially region-constrained objects

SZE CHIN NGAI

Method and system for point-to-point fast delay estimation for VLSI circuits