Inventor

NAM GI-JOON

US83 patents

⚠️ This page may combine multiple inventors who share the name “NAM GI-JOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAM GI-JOON

IBM

Clock aware placement

Analytical constraint generation for cut-based global placement

Latch clustering with proximity to local clock buffers

Fault-tolerant power-driven synthesis

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors

Constrained detailed placement

Stability metrics for placement to quantify the stability of placement algorithms

Triple and quad coloring shape layouts

Error checking and correction for NAND flash devices

Legalization of VLSI circuit placement with blockages using hierarchical row slicing

Time-driven placement and/or cloning of components for an integrated circuit

Apportioning synthesis effort for better timing closure

Post-placement cell shifting

Clustering techniques for faster and better placement of VLSI circuits

Latch placement technique for reduced clock signal skew

Power-driven synthesis under latency constraints

Creating regional routing blockages in integrated circuit design

Routing centric design closure

Electronically verifying a process flow

Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation

Error checking and correction for NAND flash devices

Detailed routability by cell placement

Time-driven placement and/or cloning of components for an integrated circuit

Memory element graph-based placement in integrated circuit design

Simultaneous multi-page commands for non-volatile memories

White space insertion for enhanced routability

Tracing and verifying a shared library using blockchain

Power driven synaptic network synthesis

Rule check heatmap prediction

Short net pin alignment for routing

Enhanced alignment for global placement in a circuit

Power staple avoidance for routing via reduction

Fault-tolerant power-driven synthesis

Dynamic SADP region generation

LS CABLE LTD

Foam coaxial cable and method for manufacturing the same

Micro coaxial cable

Asymmetrical separator and communication cable having the same

Communication cable having outside spacer and method for producing the same

ALPERT CHARLES J

Clock optimization with local clock buffer control optimization

Local objective optimization in global placement of an integrated circuit design

Post-placement cell shifting

ALPERT CHARLES JAY

Latch clustering with proximity to local clock buffers

Object placement in integrated circuit design

LG CABLE LTD

Optical cable with easily removable inner sheath

Optical fiber unit having excellent elasticity and optical cable including the same

PARK CHAN-YONG

Micro coaxial cable for high bending performance

KAZDA MICHAEL ANTHONY

Timing refinement re-routing

AGARWAL KANAK BEHARI

Multi-patterning lithography aware cell placement in integrated circuit design

XILINX INC

Method and apparatus for testing routability