Inventor
TELLEZ GUSTAVO E
US34 patents
⚠️ This page may combine multiple inventors who share the name “TELLEZ GUSTAVO E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
31 patentsUS6189132B1Feb 13, 2001
Design rule correction system and method
IBM126 citations96
US6738954B1May 18, 2004
Method for prediction random defect yields of integrated circuits with accuracy and computation time controls
IBM98 citations95
US9158885B1Oct 13, 2015
Reducing color conflicts in triple patterning lithography
IBM52 citations92
US6941528B2Sep 6, 2005
Use of a layout-optimization tool to increase the yield and reliability of VLSI designs
IBM29 citations92
US6986109B2Jan 10, 2006
Practical method for hierarchical-preserving layout optimization of integrated circuit layout
IBM38 citations90
US7076749B2Jul 11, 2006
Method and system for improving integrated circuit manufacturing productivity
IBM22 citations89
US7062729B2Jun 13, 2006
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization
IBM16 citations84
US6904575B2Jun 7, 2005
Method for improving chip yields in the presence of via flaring
IBM8 citations74
US7117456B2Oct 3, 2006
Circuit area minimization using scaling
IBM7 citations73
US9245076B2Jan 26, 2016
Orthogonal circuit element routing
IBM5 citations72
US8347257B2Jan 1, 2013
Detailed routability by cell placement
IBM5 citations72
US7337415B2Feb 26, 2008
Systematic yield in semiconductor manufacture
IBM5 citations72
US6301690B1Oct 9, 2001
Method to improve integrated circuit defect limited yield
IBM11 citations72
US11120192B1Sep 14, 2021
White space insertion for enhanced routability
IBM5 citations70
US8938702B1Jan 20, 2015
Timing driven routing for noise reduction in integrated circuit design
IBM5 citations69
US10726187B2Jul 28, 2020
Self-aligned double patterning-aware routing in chip manufacturing
IBM2 citations67
US7289659B2Oct 30, 2007
Method and apparatus for manufacturing diamond shaped chips
IBM2 citations63
US12277375B2Apr 15, 2025
Power staple avoidance for routing via reduction
IBM0 citations62
US10831972B2Nov 10, 2020
Capacity model for global routing
IBM1 citations62
US10229239B2Mar 12, 2019
Capacity model for global routing
IBM1 citations62
US7895545B2Feb 22, 2011
Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning
IBM5 citations62
US7725864B2May 25, 2010
Systematic yield in semiconductor manufacture
IBM1 citations61
US7721240B2May 18, 2010
Systematic yield in semiconductor manufacture
IBM1 citations61
US10503841B2Dec 10, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10496764B2Dec 3, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10372836B2Aug 6, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10372837B2Aug 6, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10346558B2Jul 9, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US7961932B2Jun 14, 2011
Method and apparatus for manufacturing diamond shaped chips
IBM1 citations52
US7657859B2Feb 2, 2010
Method for IC wiring yield optimization, including wire widening during and after routing
IBM1 citations52
US10606976B2Mar 31, 2020
Engineering change order aware global routing
IBM0 citations40