Inventor
RAO VISHWAS M
US13 patents
⚠️ This page may combine multiple inventors who share the name “RAO VISHWAS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
RAO VISHWAS M
5 patentsUS8539419B2Sep 17, 2013
Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
RAO VISHWAS M5 citations82
US8341573B2Dec 25, 2012
Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow
RAO VISHWAS M8 citations82
US8239805B2Aug 7, 2012
Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
RAO VISHWAS M9 citations82
US8122422B2Feb 21, 2012
Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor
RAO VISHWAS M6 citations65
US8689161B2Apr 1, 2014
Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design tools
RAO VISHWAS M1 citations50
LSI CORP
2 patentsJAMANN JOSEPH J
2 patentsUS8307324B2Nov 6, 2012
Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics
JAMANN JOSEPH J6 citations81
US8281266B2Oct 2, 2012
Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby
JAMANN JOSEPH J8 citations81
PARKER JAMES C
2 patentsUS8127264B2Feb 28, 2012
Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods
PARKER JAMES C7 citations73
US8806408B2Aug 12, 2014
Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby
PARKER JAMES C0 citations48