Inventor
EGUCHI RICHARD K
US30 patents
⚠️ This page may combine multiple inventors who share the name “EGUCHI RICHARD K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
10 patentsUS7865797B2Jan 4, 2011
Memory device with adjustable read reference based on ECC and method thereof
FREESCALE SEMICONDUCTOR INC26 citations92
US7649782B2Jan 19, 2010
Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor
FREESCALE SEMICONDUCTOR INC33 citations92
US6937047B2Aug 30, 2005
Integrated circuit with test pad structure and method of testing
FREESCALE SEMICONDUCTOR INC36 citations90
US9508397B1Nov 29, 2016
Non-volatile memory (NVM) with endurance control
FREESCALE SEMICONDUCTOR INC8 citations84
US7545679B1Jun 9, 2009
Electrical erasable programmable memory transconductance testing
FREESCALE SEMICONDUCTOR INC9 citations84
US6826103B2Nov 30, 2004
Auto-tuneable reference circuit for flash EEPROM products
FREESCALE SEMICONDUCTOR INC17 citations79
US10109356B2Oct 23, 2018
Method and apparatus for stressing a non-volatile memory
FREESCALE SEMICONDUCTOR INC2 citations71
US7782664B2Aug 24, 2010
Method for electrically trimming an NVM reference cell
FREESCALE SEMICONDUCTOR INC6 citations61
US7599236B2Oct 6, 2009
In-circuit Vt distribution bit counter for non-volatile memory devices
FREESCALE SEMICONDUCTOR INC3 citations57
US7640389B2Dec 29, 2009
Non-volatile memory having a multiple block erase mode and method therefor
FREESCALE SEMICONDUCTOR INC1 citations52
EGUCHI RICHARD K
10 patentsUS8504884B2Aug 6, 2013
Threshold voltage techniques for detecting an imminent read failure in a memory array
EGUCHI RICHARD K23 citations89
US8095836B2Jan 10, 2012
Time-based techniques for detecting an imminent read failure in a memory array
EGUCHI RICHARD K13 citations81
US9318163B2Apr 19, 2016
Robust memory start-up using clock counter
EGUCHI RICHARD K3 citations71
US9224478B2Dec 29, 2015
Temperature-based adaptive erase or program parallelism
EGUCHI RICHARD K6 citations71
US9318161B2Apr 19, 2016
Non-volatile memory robust start-up using analog-to-digital converter
EGUCHI RICHARD K2 citations62
US8432752B2Apr 30, 2013
Adaptive write procedures for non-volatile memory using verify read
EGUCHI RICHARD K2 citations62
US8572445B2Oct 29, 2013
Non-volatile memory (NVM) with imminent error prediction
EGUCHI RICHARD K4 citations58
US8289773B2Oct 16, 2012
Non-volatile memory (NVM) erase operation with brownout recovery technique
EGUCHI RICHARD K3 citations58
US8977914B2Mar 10, 2015
Stress-based techniques for detecting an imminent read failure in a non-volatile memory array
EGUCHI RICHARD K1 citations52
US8782478B2Jul 15, 2014
Non-volatile memory (NVM) with imminent error prediction
EGUCHI RICHARD K1 citations45
HE CHEN
6 patentsUS8687428B2Apr 1, 2014
Built-in self trim for non-volatile memory reference current
HE CHEN9 citations83
US9082510B2Jul 14, 2015
Non-volatile memory (NVM) with adaptive write operations
HE CHEN4 citations73
US8516213B2Aug 20, 2013
Method and apparatus for EEPROM emulation for preventing data loss in the event of a flash block failure
HE CHEN5 citations69
US8509001B2Aug 13, 2013
Adaptive write procedures for non-volatile memory
HE CHEN4 citations62
US8427877B2Apr 23, 2013
Digital method to obtain the I-V curves of NVM bitcells
HE CHEN2 citations62
US9076508B2Jul 7, 2015
Built-in self trim for non-volatile memory reference current
HE CHEN0 citations51
WEILEMANN II JON W
3 patentsUS9329921B2May 3, 2016
Imminent read failure detection using high/low read voltage levels
WEILEMANN II JON W2 citations58
US9329933B2May 3, 2016
Imminent read failure detection based upon changes in error voltage windows for NVM cells
WEILEMANN II JON W1 citations47
US9329932B2May 3, 2016
Imminent read failure detection based upon unacceptable wear for NVM cells
WEILEMANN II JON W1 citations47