Inventor
CHAWARE RAGHUNANDAN
US21 patents
⚠️ This page may combine multiple inventors who share the name “CHAWARE RAGHUNANDAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
13 patentsUS9418909B1Aug 16, 2016
Stacked silicon package assembly having enhanced lid adhesion
XILINX INC28 citations94
US9865567B1Jan 9, 2018
Heterogeneous integration of integrated circuit device and companion device
XILINX INC33 citations93
US7863092B1Jan 4, 2011
Low cost bumping and bonding method for stacked die
XILINX INC26 citations92
US7906857B1Mar 15, 2011
Molded integrated circuit package and method of forming a molded integrated circuit package
XILINX INC30 citations89
US10840192B1Nov 17, 2020
Stacked silicon package assembly having enhanced stiffener
XILINX INC12 citations82
US9761533B2Sep 12, 2017
Interposer-less stack die interconnect
XILINX INC3 citations73
US10032682B1Jul 24, 2018
Multi-die wafer-level test and assembly without comprehensive individual die singulation
XILINX INC3 citations72
US9989572B1Jun 5, 2018
Method and apparatus for testing interposer dies prior to assembly
XILINX INC5 citations72
US9385106B1Jul 5, 2016
Method for providing charge protection to one or more dies during formation of a stacked silicon device
XILINX INC5 citations72
US11075117B2Jul 27, 2021
Die singulation and stacked device structures
XILINX INC1 citations62
US10204841B1Feb 12, 2019
Temporary connection traces for wafer sort testing
XILINX INC1 citations62
US8900987B1Dec 2, 2014
Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices
XILINX INC3 citations61
US9341668B1May 17, 2016
Integrated circuit package testing
XILINX INC1 citations49