Inventor
NONDHASITTHICHAI SOMCHAI
TH36 patents
⚠️ This page may combine multiple inventors who share the name “NONDHASITTHICHAI SOMCHAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
UTAC THAI LTD
11 patentsUS7327017B2Feb 5, 2008
Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound
UTAC THAI LTD40 citations94
US8013437B1Sep 6, 2011
Package with heat transfer
UTAC THAI LTD9 citations84
US7790512B1Sep 7, 2010
Molded leadframe substrate semiconductor package
UTAC THAI LTD14 citations84
US8704381B2Apr 22, 2014
Very extremely thin semiconductor package
UTAC THAI LTD1 citations63
US7572168B1Aug 11, 2009
Method and apparatus for high speed singulation
UTAC THAI LTD6 citations54
US9818676B2Nov 14, 2017
Singulation method for semiconductor package with plating on side of connectors
UTAC THAI LTD0 citations52
US9093486B2Jul 28, 2015
Molded leadframe substrate semiconductor package
UTAC THAI LTD0 citations52
US8685794B2Apr 1, 2014
Lead frame land grid array with routing connector trace under unit
UTAC THAI LTD0 citations49
US8652879B2Feb 18, 2014
Lead frame ball grid array with traces under die
UTAC THAI LTD1 citations49
US7922877B2Apr 12, 2011
Method and apparatus for plating a semiconductor package
UTAC THAI LTD0 citations44
US7718522B2May 18, 2010
Method and apparatus for plating a semiconductor package
UTAC THAI LTD0 citations44
NONDHASITTHICHAI SOMCHAI
9 patentsUS9099317B2Aug 4, 2015
Method for forming lead frame land grid array
NONDHASITTHICHAI SOMCHAI4 citations84
US9082607B1Jul 14, 2015
Molded leadframe substrate semiconductor package
NONDHASITTHICHAI SOMCHAI4 citations84
US8575762B2Nov 5, 2013
Very extremely thin semiconductor package
NONDHASITTHICHAI SOMCHAI4 citations73
US9711343B1Jul 18, 2017
Molded leadframe substrate semiconductor package
NONDHASITTHICHAI SOMCHAI1 citations62
US8492906B2Jul 23, 2013
Lead frame ball grid array with traces under die
NONDHASITTHICHAI SOMCHAI2 citations59
US8487451B2Jul 16, 2013
Lead frame land grid array with routing connector trace under unit
NONDHASITTHICHAI SOMCHAI2 citations59
US9899208B2Feb 20, 2018
Molded leadframe substrate semiconductor package
NONDHASITTHICHAI SOMCHAI0 citations52
US9196470B1Nov 24, 2015
Molded leadframe substrate semiconductor package
NONDHASITTHICHAI SOMCHAI0 citations52
US9099294B1Aug 4, 2015
Molded leadframe substrate semiconductor package
NONDHASITTHICHAI SOMCHAI0 citations52
SIRINORAKUL SARAVUTH
8 patentsUS8063470B1Nov 22, 2011
Method and apparatus for no lead semiconductor package
SIRINORAKUL SARAVUTH41 citations92
US8338922B1Dec 25, 2012
Molded leadframe substrate semiconductor package
SIRINORAKUL SARAVUTH8 citations84
US8129229B1Mar 6, 2012
Method of manufacturing semiconductor package containing flip-chip arrangement
SIRINORAKUL SARAVUTH18 citations84
US9761435B1Sep 12, 2017
Flip chip cavity package
SIRINORAKUL SARAVUTH4 citations73
US9349679B2May 24, 2016
Singulation method for semiconductor package with plating on side of connectors
SIRINORAKUL SARAVUTH3 citations73
US8125077B2Feb 28, 2012
Package with heat transfer
SIRINORAKUL SARAVUTH3 citations63
US8071426B2Dec 6, 2011
Method and apparatus for no lead semiconductor package
SIRINORAKUL SARAVUTH3 citations63
US9947605B2Apr 17, 2018
Flip chip cavity package
SIRINORAKUL SARAVUTH0 citations42
NS ELECTRONICS BANGKOK 1993 LT
4 patentsUS7060535B1Jun 13, 2006
Flat no-lead semiconductor die package including stud terminals
NS ELECTRONICS BANGKOK 1993 LT179 citations96
US7205180B1Apr 17, 2007
Process of fabricating semiconductor packages using leadframes roughened with chemical etchant
NS ELECTRONICS BANGKOK 1993 LT60 citations95
US7049683B1May 23, 2006
Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound
NS ELECTRONICS BANGKOK 1993 LT40 citations94
US7153724B1Dec 26, 2006
Method of fabricating no-lead package for semiconductor die with half-etched leadframe
NS ELECTRONICS BANGKOK 1993 LT36 citations90
UTAC HEADQUARTERS PTE LTD
4 patentsUS9741642B1Aug 22, 2017
Semiconductor package with partial plating on contact side surfaces
UTAC HEADQUARTERS PTE LTD8 citations81
US9773722B1Sep 26, 2017
Semiconductor package with partial plating on contact side surfaces
UTAC HEADQUARTERS PTE LTD4 citations71
US10515878B1Dec 24, 2019
Semiconductor package with partial plating on contact side surfaces
UTAC HEADQUARTERS PTE LTD3 citations70
US10204850B1Feb 12, 2019
Semiconductor package with partial plating on contact side surfaces
UTAC HEADQUARTERS PTE LTD0 citations50