Inventor
QUON ROGER A
US53 patents
⚠️ This page may combine multiple inventors who share the name “QUON ROGER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
40 patentsUS9934970B1Apr 3, 2018
Self aligned pattern formation post spacer etchback in tight pitch configurations
IBM22 citations94
US9761655B1Sep 12, 2017
Stacked planar capacitors with scaled EOT
IBM36 citations94
US9991156B2Jun 5, 2018
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
IBM15 citations93
US9786603B1Oct 10, 2017
Surface nitridation in metal interconnects
IBM14 citations93
US9859218B1Jan 2, 2018
Selective surface modification of interconnect structures
IBM16 citations92
US10529569B2Jan 7, 2020
Self aligned pattern formation post spacer etchback in tight pitch configurations
IBM5 citations84
US9779944B1Oct 3, 2017
Method and structure for cut material selection
IBM17 citations84
US9607886B1Mar 28, 2017
Self aligned conductive lines with relaxed overlay
IBM6 citations84
US7629264B2Dec 8, 2009
Structure and method for hybrid tungsten copper metal contact
IBM18 citations84
US7144490B2Dec 5, 2006
Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer
IBM14 citations84
US9899317B1Feb 20, 2018
Nitridization for semiconductor structures
IBM8 citations82
US7170187B2Jan 30, 2007
Low stress conductive polymer bump
IBM11 citations82
US11133216B2Sep 28, 2021
Interconnect structure
IBM3 citations73
US10957583B2Mar 23, 2021
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
IBM1 citations73
US10699945B2Jun 30, 2020
Back end of line integration for interconnects
IBM5 citations73
US10546774B2Jan 28, 2020
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
IBM3 citations73
US10128147B2Nov 13, 2018
Interconnect structure
IBM2 citations73
US10121661B2Nov 6, 2018
Self aligned pattern formation post spacer etchback in tight pitch configurations
IBM2 citations73
US9852946B1Dec 26, 2017
Self aligned conductive lines
IBM2 citations73
US9786554B1Oct 10, 2017
Self aligned conductive lines
IBM5 citations73
US9773700B1Sep 26, 2017
Aligning conductive vias with trenches
IBM5 citations73
US6995475B2Feb 7, 2006
I/C chip suitable for wire bonding
IBM9 citations73
US7442878B2Oct 28, 2008
Low stress conductive polymer bump
IBM7 citations72
US7923836B2Apr 12, 2011
BLM structure for application to copper pad
IBM4 citations63
US7473997B2Jan 6, 2009
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
IBM4 citations62
US6992389B2Jan 31, 2006
Barrier for interconnect and method
IBM4 citations61
US7926006B2Apr 12, 2011
Variable fill and cheese for mitigation of BEOL topography
IBM4 citations60
US8026166B2Sep 27, 2011
Interconnect structures comprising capping layers with low dielectric constants and methods of making the same
IBM3 citations59
US10615116B2Apr 7, 2020
Surface nitridation in metal interconnects
IBM0 citations52
US10529621B2Jan 7, 2020
Modulating the microstructure of metallic interconnect structures
IBM0 citations52
US10395985B2Aug 27, 2019
Self aligned conductive lines with relaxed overlay
IBM0 citations52
US10373909B2Aug 6, 2019
Selective surface modification of interconnect structures
IBM0 citations52
US10361153B2Jul 23, 2019
Surface nitridation in metal interconnects
IBM0 citations52
US10256185B2Apr 9, 2019
Nitridization for semiconductor structures
IBM0 citations52
US10249532B2Apr 2, 2019
Modulating the microstructure of metallic interconnect structures
IBM0 citations52
US10083864B2Sep 25, 2018
Self aligned conductive lines with relaxed overlay
IBM0 citations52
US10068846B2Sep 4, 2018
Surface nitridation in metal interconnects
IBM0 citations52
US9972533B2May 15, 2018
Aligning conductive vias with trenches
IBM0 citations52
US9953864B2Apr 24, 2018
Interconnect structure
IBM0 citations52
US9911647B2Mar 6, 2018
Self aligned conductive lines
IBM1 citations52
GLOBALFOUNDRIES INC
3 patentsUS9589911B1Mar 7, 2017
Integrated circuit structure with metal crack stop and methods of forming same
GLOBALFOUNDRIES INC8 citations82
US9589912B1Mar 7, 2017
Integrated circuit structure with crack stop and method of forming same
GLOBALFOUNDRIES INC5 citations71
US9601513B1Mar 21, 2017
Subsurface wires of integrated chip and methods of forming
GLOBALFOUNDRIES INC1 citations52
CLEVENGER LAWRENCE A
3 patentsUS8574950B2Nov 5, 2013
Electrically contactable grids manufacture
CLEVENGER LAWRENCE A7 citations81
US8802990B2Aug 12, 2014
Self-aligned nano-scale device with parallel plate electrodes
CLEVENGER LAWRENCE A1 citations52
US8476530B2Jul 2, 2013
Self-aligned nano-scale device with parallel plate electrodes
CLEVENGER LAWRENCE A0 citations52
TESSERA LLC
2 patentsTESSERA INC
1 patentSAMSUNG ELECTRONICS CO LTD
1 patentShowing the top 50 of 53 patents by PatentIndex Score.