Inventor
OKAZAKI ATSUYA
JP32 patents
⚠️ This page may combine multiple inventors who share the name “OKAZAKI ATSUYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
26 patentsUS10169237B2Jan 1, 2019
Identification of a computing device accessing a shared memory
IBM4 citations84
US10339444B2Jul 2, 2019
Monitoring potential of neuron circuits
IBM3 citations73
US10319444B2Jun 11, 2019
Memory data randomizer
IBM1 citations73
US10289950B2May 14, 2019
Monitoring potential of neuron circuits
IBM2 citations73
US10490273B1Nov 26, 2019
Linearly weight updatable CMOS synaptic array without cell location dependence
IBM4 citations71
US12438530B2Oct 7, 2025
Ir drop compensation
IBM0 citations62
US11789857B2Oct 17, 2023
Data transfer with continuous weighted PPM duration signal
IBM0 citations62
US11270191B2Mar 8, 2022
On-chip Poisson spike generation
IBM0 citations62
US11163681B2Nov 2, 2021
Identification of a computing device accessing a shared memory
IBM0 citations62
US9940237B2Apr 10, 2018
Identification of a computing device accessing a shared memory
IBM1 citations62
US9928175B2Mar 27, 2018
Identification of a computing device accessing a shared memory
IBM1 citations62
US9066289B2Jun 23, 2015
Packet communication system, communication method and program
IBM3 citations62
US11087811B1Aug 10, 2021
NVM synaptic element with gradual reset capability
IBM0 citations60
US11763139B2Sep 19, 2023
Neuromorphic chip for updating precise synaptic weight values
IBM0 citations52
US11475946B2Oct 18, 2022
Synapse weight update compensation
IBM0 citations52
US10740673B2Aug 11, 2020
Scalable refresh for asymmetric non-volatile memory-based neuromorphic circuits
IBM0 citations52
US10573387B2Feb 25, 2020
Memory data randomizer
IBM0 citations52
US10559358B2Feb 11, 2020
Memory data randomizer
IBM0 citations52
US10445640B1Oct 15, 2019
Scalable refresh for asymmetric non-volatile memory-based neuromorphic circuits
IBM0 citations52
US10241917B2Mar 26, 2019
Identification of a computing device accessing a shared memory
IBM0 citations52
US10095541B2Oct 9, 2018
Executing memory access while performing task switching
IBM0 citations51
US8913458B2Dec 16, 2014
Integrity check of measured signal trace data
IBM0 citations51
US8902694B2Dec 2, 2014
Integrity check of measured signal trace data
IBM1 citations51
US10672471B2Jun 2, 2020
Linearly weight updatable CMOS synaptic array without cell location dependence
IBM0 citations50
US8346080B2Jan 1, 2013
Optical network system and memory access method
IBM0 citations41
US9910789B2Mar 6, 2018
Electrical and optical memory access
IBM0 citations34
KATAYAMA YASUNAO
2 patentsUS8644667B2Feb 4, 2014
Backplane structure allowing setting of equal peer-to-peer communication distance between two blades arbitrarily inserted into a plurality of fixedly arranged slots
KATAYAMA YASUNAO3 citations62
US8442028B2May 14, 2013
Packet communication system, communication method and program
KATAYAMA YASUNAO2 citations62