Inventor

BUI DUC QUANG

US57 patents

⚠️ This page may combine multiple inventors who share the name “BUI DUC QUANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUI DUC QUANG

TEXAS INSTRUMENTS INC

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Tracking streaming engine vector predicates to control processor execution

Method and apparatus for vector permutation

Tracking streaming engine vector predicates to control processor execution

Highly integrated scalable, flexible DSP megamodule architecture

Butterfly network on load data return

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Predication methods for vector processors

Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS cellular systems

Streaming address generation

Vector load and duplicate operations

Controlling the number of powered vector lanes via a register field

Tracking streaming engine vector predicates to control processor execution

Method and apparatus for permuting streamed data elements

Highly integrated scalable, flexible DSP megamodule architecture

System and method to control the number of active vector lanes in a processor

Method and apparatus for permuting streamed data elements

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Method and apparatus for permuting streamed data elements

System and method for addressing data in memory

Tracking streaming engine vector predicates to control processor execution

Method and apparatus for vector permutation

Vector SIMD VLIW data path architecture

System and method to control the number of active vector lanes in a processor

Controlling the number of powered vector lanes via a register field

System and method for addressing data in memory

System and method to control the number of active vector lanes in a processor

Controlling the number of powered vector lanes via a register field

Register file structures combining vector and scalar data with global and local accesses

System and method for predication handling

Vector SIMD VLIW data path architecture

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Butterfly network on load data return

Forming constant extensions in the same execute packet in a VLIW processor

Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof

Quick clearing of registers

Streaming address generation

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Vector SIMD VLIW data path architecture

Butterfly network on load data return

Vector load and duplicate operations

Quick clearing of registers

Method for forming constant extensions in the same execute packet in a VLIW processor

Streaming address generation

Vector SIMD VLIW data path architecture

Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof

System and method for predication handling

Predication methods for vector processors

IBM

Method and system for interchanging operands during complex instruction execution in a data processing system