Inventor

BHUNIA SWARUP

IN45 patents

⚠️ This page may combine multiple inventors who share the name “BHUNIA SWARUP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHUNIA SWARUP

UNIV FLORIDA

System and method for charging a network of mobile battery-operated units on-the-go

Multi-level battery systems for battery-operated entities, methods for rapid charge transfer therebetween, and methods for optimizing entity routing and network charge distribution

Vanishing via for hardware IP protection from reverse engineering

SARO: scalable attack-resistant obfuscation of logic circuits

Hardware intellectual property protection through provably secure state-space obfuscation

Trojan insertion tool

System and method for a battery on wheels (BoW) for charging mobile battery-operated units

System and method for closed-loop active sensing and protection against airborne pathogens

Reconfigurable system-on-chip security architecture

Nano-electro-mechanical tags for identification and authentication

Multi-purpose context-aware bump (CAB) supporting dynamic adaptation of form factors and functionality

Nano-electro-mechanical labels and encoder

Steganography of hardware intellectual property

Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs

Learning guided obfuscation framework for hardware IP protection

Electromagnetic based secure contact-less integrity verification of hardware and/or software for integrated circuits

System and method for hand-held NQR-based in-field screening of substances

Predictive joint compression and encryption for images and videos

Establishing trust in untrusted IC testing and provisioning environment

Uniquified FPGA virtualization approach to hardware security

Systems and methods for machine intelligence based malicious design alteration insertion

Decommissioning and erasing entropy in microelectronic systems

Removal of hardware intellectual property and programmable replacement

Timed unlocking and locking of hardware intellectual properties

Smart infrastructures and first-responder network for security and safety hazards

Programmable application-specific array for protecting confidentiality and integrity of hardware IPS

Side-channel signature based PCB authentication using JTAG architecture and a challenge-response mechanism

Drone-based administration of remotely located instruments and gadgets

Memory in logic physical unclonable function

Defense of JTAG I/O network

Look-up table-based in-memory computing system

Multi-layered framework for security of integrated circuits

Framework for obfuscation based watermarking

Invisible scan architecture for secure testing of digital designs

UNIV CASE WESTERN RESERVE

Defense against counterfeiting using antifuses

Nanoelectromechanical antifuse and related systems

Tagging of materials and objects and analysis for authentication thereof

Multi-modal spectroscopic analysis

CLEVELAND CLINIC FOUND

Bladder event detection for diagnosis of urinary incontinence or treatment of lower urinary tract dysfunction

Bladder event detection for diagnosis of urinary incontinence or treatment of lower urinary tract dysfunction

PURDUE RESEARCH FOUNDATION

Synthesis approach for active leakage power reduction using dynamic supply gating

Apparatus and methods for determining memory device faults

STC UNM

Systems and methods for generating physically unclonable functions from non-volatile memory cells

CHAKRABORTY RAJAT SUBHRA

Protection of intellectual property cores through a design flow

PURDUE RES FOUNDATION PURDUE U

Low power scan design and delay fault testing technique using first level supply gating