Inventor

SAPORITO ANTHONY

US147 patents

⚠️ This page may combine multiple inventors who share the name “SAPORITO ANTHONY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAPORITO ANTHONY

IBM

Fingerprint-initiated trace extraction

Error accumulation register, error accumulation method, and error accumulation system

System and method for providing processor recovery in a multi-core system

Reducing cache transfer overhead in a system

Accuracy of operand store compare prediction using confidence counter

Dynamic thread sharing in branch prediction structures

Automated compiler operation verification

Accuracy of operand store compare prediction using confidence counter

Restricting processing within a processor to facilitate transaction completion

System and method for providing asynchronous dynamic millicode entry prediction

Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor

Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class

Translation support for a virtual cache

Reducing cache transfer overhead in a system

Cache structure using a logical directory

Determining the effectiveness of prefetch instructions

Reducing cache transfer overhead in a system

Temporarily suppressing processing of a restrained storage operand request

Generating and verifying hardware instruction traces including memory data contents

Load logical and shift guarded instruction

Cache structure using a logical directory

Reducing cache transfer overhead in a system

Reducing cache transfer overhead in a system

Temporarily suppressing processing of a restrained storage operand request

Run-time instrumentation of guarded storage event processing

Identifying processor attributes based on detecting a guarded storage event

Spin loop delay instruction

Reducing over-purging of structures associated with address translation using an array of tags

Dynamic thread sharing in branch prediction structures

Host page management using active guest page table indicators

Reducing over-purging of structures associated with address translation

Managing a prefetch queue based on priority indications of prefetch requests

Reducing purging of structures associated with address translation

Dynamic thread sharing in branch prediction structures

Behavior based code recompilation triggering scheme

Software instructed dynamic branch history pattern adjustment

Single thread cache miss rate estimation

Accuracy of operand store compare prediction using confidence counter

Variable updates of branch prediction states

Scheme for verifying the effects of program optimizations

Fingerprint-based branch prediction

Fingerprint-based code version selection

Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch

Program event recording storage alteration processing for a neural network accelerator instruction

Operating different processor cache levels

Cache miss thread balancing

Making precise operand-store-compare predictions to avoid false dependencies

ALEXANDER KHARY J

System and method for Controlling restarting of instruction fetching using speculative address computations

BONANNO JAMES J

Selectively blocking branch prediction for a predetermined number of instructions

PRASKY BRIAN R

Cache set selective power up